Xilinx Verification Engineer Interview Questions | Glassdoor

Xilinx Verification Engineer Interview Questions

Updated Sep 28, 2017
5 Interview Reviews

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Verification Engineer Interview

Anonymous Interview Candidate in India, TX
No Offer
Positive Experience
Average Interview

Application

I applied online. The process took 2 weeks. I interviewed at Xilinx (India, TX) in March 2017.

Interview

I had applied for the position on web site. Since my skills matched with what they were looking for I got a call. The interview was basic, just questions on my resume. very good and focused on future role
focused much on soc point of view

Interview Questions

Other Interview Reviews for Xilinx

  1. Helpful (4)  

    Verification Engineer Interview

    Anonymous Interview Candidate in San Jose, CA
    No Offer
    Negative Experience
    Easy Interview

    Application

    I applied through other source. The process took 1 day. I interviewed at Xilinx (San Jose, CA) in October 2011.

    Interview

    Interviewed with PCIe team. Female engineer from Colorado asked me a reasonable nested loop question then proceeded to interrupt me at least 8 times. After the 5th interruption I gave up solving the problem and did my best not to make a scene. She continued to interrupt me then asked very condescending questions in a very sarcastic tone. I have never met, seen, or heard of a more disrespectful interviewer during my time as a professional engineer. I later met an engineer from Xilinx (Malaysia) who worked with this woman and confirmed my assessment of her. In my opinion there was an additional engineer who was insulting. He asked me very simple questions then finished with a trick question that I didn't realize until the interview was over. I'm certain that I have designed more async interfaces than the entire team combined but I'm sure he told everyone that I missed the trick async question since he insisted on taking a picture of my solution. They were typical arrogant engineers. I couldn't be more please to not be working for this team. Lastly, the position was for a SystemVerilog OVM verification engineer working on PCIe gen 3. NOT one single question on systemverilog, OVM, or PCIe. Not one.

    Interview Questions

    • how do you help someone who put a battery in a device backwards....yes, this was a real question   Answer Question
    • do a sub string seach of a string using nested loops   Answer Question

  2.  

    Verification Engineer Interview

    Anonymous Interview Candidate in Edinburgh, Scotland (UK)
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied online. I interviewed at Xilinx (Edinburgh, Scotland (UK)) in June 2017.

    Interview

    The interview process involved a telephonic interview and a face to face interview. They asked briefly about my qualification and skills in the telephonic Interview. In the face to face interview the technical round was involved with asking few questions on coding in verilog and system verilog.

    Interview Questions

    • They gave me few written programmes and asked me to explain the programme flow   1 Answer
  3.  

    Verification Engineer Interview

    Anonymous Employee
    Accepted Offer
    Positive Experience

    Application

    I applied online. The process took 2+ weeks. I interviewed at Xilinx.

    Interview

    It is very exhausting. 9 interviews . but the interviews were fair.

    Interview Questions

    Negotiation

    not much to negotiate


  4.  

    Verification Engineer Interview

    Anonymous Employee
    Accepted Offer

    Interview

    Many script related questions (such as perl, unix, etc). Need some basic understanding of fpga/logic design

    Interview Questions


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