Analog Engineer Interview Questions | Glassdoor

Analog Engineer Interview Questions

102

Analog engineer interview questions shared by candidates

Top Interview Questions

Sort: RelevancePopular Date

Nov 21, 2013
 Q2: A pnp transistor with its base connected to a voltage source, the V source is connected to a +10V source. The emitter of the transistor is connected to a resistance, and then to the same +10V source. The collector side is connected to a capacitor, which is not charged at t=0-. Given the graph of Vsource = 10 V stepping up at t = 0 to further, draw the graph of Vout. Vout is between the point of collector and capacitor. 2 AnswersANS: Vout should be constantly -10V until t=0, and will hit V=0 V linearly from V=-10 V after t=0.Hi, Can you explain why it linearly increases? Are you assuming that Collector is tied to -10V? The pnp transistor is completely cutoff for the given biasing. The only way the capacitor is going to charge is through leakage currents. It is very slow and takes a lot of time. Please advise me if my analysis is correct.

Analog & Mixed-Signal IC Design Engineer at Qualcomm was asked...

Jun 26, 2012
 How to make sure the 2-stage opamp is stable? How does the compensation work?5 AnswersUse compensation capacitor. Look up pole splitting which uses Miller effect on the capacitor.By constructing current mirror circuit using op-amp 741 through compensation resistor at the feedback side. Finally the input and output of the op-amp gets compensated.Using Miller compensation. A compensation capacitor across the 2nd stage to create pole splitting. A series resistor to the cap might be needed to solve the rhp zero problemShow More ResponsesUsing compensation capacitor, which makes the low frequency pole's frequency become lower and high frequency pole's frequency higher, so OPmap is more stable.Using compensation network including capacitor and resistor and monitoring the phase margin and gain margin as well.

Electrical Engineer, Analog at Intel Corporation was asked...

Jan 25, 2011
 Change the current mirror to a resistor for a diff amp. What is the result?1 AnswerThe opamp will be no more diff-2-single ended. Mismatch in the resistors introduce o/p offset voltage. would need common-mode feedback circuit to fix it. PSRR will be worse. Advantage: High speed ( similar to CML)

Feb 15, 2011
 Can you draw a circuit to bias the gate of a cascode device? (No mention of supply limitation, threshold voltages, care in tracking PVT variations, or anything else. Just, draw a circuit to bias the gate of a cascode device.)1 AnswerI drew a resistive voltage divider and was then told, "That won't track over process." I then drew a replica bias structure (diode connected devices that matched the original amplifier) to which I was told, "How are you going to use that if your supply is only 1V?" I then drew a diode connected device with a W/L which was 1/4 the value of the device whose gate needed bias. Was then told, "That's right, but we usually use 1/5 or 1/6 for body effect compensation." Answered the question asked each time but they wanted a very specific answer from the beginning.

Analog Engineer at Lutron was asked...

Feb 1, 2010
 Brian teasers - the coins , the 3 light bulbs 1 AnswerLook at any brian teasers / lateral thinking website

Analog IC Design Engineer at Fairchild Semiconductor was asked...

Oct 19, 2014
 We have lunch right now, you are welcome to join us1 AnswerYou have to say Yes...Don't say No and find an excuse

Analog IC Design Engineer at Texas Instruments was asked...

Aug 12, 2012
 TI Fellow asked me this question: If you're hired, your job will be to design a power supply, that I haven't been able to figure out. How will you go about it?1 AnswerI responded with some ideas, and he must have liked them.

Analog Design Engineer at Marvell Semiconductor was asked...

Apr 4, 2012
 Tell me about your project (from the resume) - Temperature Sensor IC Design1 AnswerI explain using CMOS which i had done. Cudnt explain them properly using BJT (same circuit). PTAT and CTAT, K factor were asked.

Analog Design Engineer/Power Management at Qualcomm was asked...

Mar 12, 2012
 why is matching required?1 AnswerMatching in MOSFET transistor inverters is necessary because the electrons that move in the NMOS transistor move at a faster rate than the holes that move in the PMOS transistor. This means when a signal is received, the NMOS will react before the PMOS. To equalize this, they transistors must be matched (by adjusting their widths) so that their transition times are the same.

Analog Product Development Engineer at Microchip Technology was asked...

Mar 30, 2011
 What is the biasing voltage of Diode1 Answer0.7 V
110 of 102 Interview Questions

More