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Analog Engineer Interview Questions

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Q2: A pnp transistor with its base connected to a voltage source, the V source is connected to a +10V source. The emitter of the transistor is connected to a resistance, and then to the same +10V source. The collector side is connected to a capacitor, which is not charged at t=0-. Given the graph of Vsource = 10 V stepping up at t = 0 to further, draw the graph of Vout. Vout is between the point of collector and capacitor.

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ANS: Vout should be constantly -10V until t=0, and will hit V=0 V linearly from V=-10 V after t=0.

Hi, Can you explain why it linearly increases? Are you assuming that Collector is tied to -10V? The pnp transistor is completely cutoff for the given biasing. The only way the capacitor is going to charge is through leakage currents. It is very slow and takes a lot of time. Please advise me if my analysis is correct.

How to make sure the 2-stage opamp is stable? How does the compensation work?

5 Answers

Change the current mirror to a resistor for a diff amp. What is the result?

1 Answer

Can you draw a circuit to bias the gate of a cascode device? (No mention of supply limitation, threshold voltages, care in tracking PVT variations, or anything else. Just, draw a circuit to bias the gate of a cascode device.)

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Brian teasers - the coins , the 3 light bulbs

1 Answer

We have lunch right now, you are welcome to join us

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TI Fellow asked me this question: If you're hired, your job will be to design a power supply, that I haven't been able to figure out. How will you go about it?

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Tell me about your project (from the resume) - Temperature Sensor IC Design

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why is matching required?

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What is the biasing voltage of Diode

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