Analog Mixed Signal Design Engineer Interview Questions
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Analog Mixed Signal Design Engineer interview questions shared by candidates
How to make sure the 2-stage opamp is stable? How does the compensation work?
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Using Miller compensation. A compensation capacitor across the 2nd stage to create pole splitting. A series resistor to the cap might be needed to solve the rhp zero problem Less
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Using compensation capacitor, which makes the low frequency pole's frequency become lower and high frequency pole's frequency higher, so OPmap is more stable. Less
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Using compensation network including capacitor and resistor and monitoring the phase margin and gain margin as well. Less
What is the difference between == and === ? What is the use of reg in verilog?
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The main difference is === operator not allowed to compare two different variable to compare such as int and string, if you compare it will return false, while == will allow to compare. reg use to define register in verilog, It can be used as a storing number or bit. Less
Very basic questions(which were easy if we come out of college or recent grad but very unexpected for an experienced candidate, since we don't need to do all that at hand calculation level everytime), Although figured out most of them but couldn't give satisfactory answers as I was rusty in few topics(my mistake too, could review those concepts because of poor time management) The recruiter was pretty rude too, which again was kind of demotivating, especially when we try to figure out things on which we turned rusty.
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Although easy questions but things didn't work out, maybe mix of nervousness as it was (The INTEL), rude recruiter, rusty topics for me and so on. Less
1. Basic questions around transistors - particularly large W/L ratio ones. 2. A couple of circuits with pmos and nmos in a current mirror configuration - I was asked what would be the node voltages as a function of input to one of the transistor's gate. 3. Layout/cross section of inverter and small signal model of MOSFET
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Start off with writing Ids equations in different regimes and check conditions for finite current given a large W/L transistor. Be thorough with the absolute basic stuff! Less
The position was for MS/ Ph.D. with 2 years of experience, I was an MS graduate with 2 years exp. They needed someone who worked heavily on SerDes designing with various Analog/Mixed-signal circuits in the SerDes Tx and Rx block. As I was working on the same project, they were interested in my profile for the interview. The interview consisted of 8 rounds, started at 9 AM and ended at 4:30 PM. Qs are as follows: -Single and two stage op amp basic, gain, impedance calculation -Compensation technique(Miller, in any other as well) -Gain and Rout calculation for Differential pair, Diode connected based circuits -Cascode and cascade circuits -CML circuit (buffer and Latch), factors to consider while designing CML buffer and latches (W/L, I bias, R out, etc) -How tail current/impedence affect the output and circuit performance -Arch of SerDes Rx and Tx, about each module in it, draw the complete architecture -Parallel to serial converter, serial to parallel converter, circuit design -VGA and PA circuit of SerDes Rx -DFE (Rx), FFE (Tx) working -CDR module (both Analog and digital type) -Phase Frequency detector circuit design, why PFD over PD for CDR design -PLL and CDR differences and module level design -VCO design ( 30 GHz LC based in my project) -Inductor layout design, Q factor= (2X Pi X F X L)/R, metal used (Metal 6), center taped -architecture design, respective calculations, Sonnet tool -Simulink -Matlab coding for Mixed-signal analysis -Verilog-AMS in cadence -Negative setup and hold time -Why nand over nor -Setup and hold time -Op-amp as integrator, differentiator, respective equations -Widler bandgap reference circuit design -BJT based question and respective circuit analysis(KCL/KVL) -Linear voltage regulator (my project) complete analysis and design -Verilog basic and write a few modules code -How to remove/reduce noises in analog/mixed-signal design world (about decoupling -capacitors and linear voltage regulators), noise analysis. -Tools used to validate the CDR design and TX, RX blocks of theSerDes. It was a tough interview which is obvious for such a good position, well-experienced team. Some engineers who interviewed me were nice, while a few were very rude which is common(I had faced the similar type of rude engineers in past while being interviewed for other positions in Intel) but on the bright side, there are other engineers who do care and try to understand the candidates without directly judging them.
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I did okay but due to long interview hours, I couldn't do up to the mark. Felt demotivated with some rounds while tried my best to regain my focus and did other rounds pretty well. It was a rollercoaster but nice experience. Less
