# ASIC Design Engineer Interview Questions

ASIC design engineer interview questions shared by candidates

## Top Interview Questions

design a full adder with 2-1 mux Full Adder can be implemented by two half adder; a half adder can be implemented by a XOR and AND gate. XOR and AND gate can be implemented by 2:1 MUX. full adder can be got by 2 half adders and one OR gate; one half adder can be got by XOR, AND. Therefore, we need only OR, AND, XOR. All these three gates can be got by using MUX.? Can be implemented using 8 Muxes. Show More Responses |

design a combinational circuit which counts the number of 1s in a 7-bit input . |

Design a divide by 3 counter. Bonus for 50% duty cycle |

which is hard to fix -- setup violation or hold violation? And why? |

Complete the C function (body) that uses recursion to determine if the string is a palindrome |

The I-V characteristic and five regions of MOS operation. |

frequency divide by 3 clk circuit |

List all possible ways to minimize the power dissipation of an ASIC chip. |

There are 8 bits inputs ,only use full adder to detect how many logic 1's |

is there any benefit to use cache if there is read miss for every access? |

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