# Asic design engineer Interview Questions

asic design engineer interview questions shared by candidates

## Top Interview Questions

design a full adder with 2-1 mux Full Adder can be implemented by two half adder; a half adder can be implemented by a XOR and AND gate. XOR and AND gate can be implemented by 2:1 MUX. full adder can be got by 2 half adders and one OR gate; one half adder can be got by XOR, AND. Therefore, we need only OR, AND, XOR. All these three gates can be got by using MUX.? Can be implemented using 8 Muxes. Show More Responses |

design a combinational circuit which counts the number of 1s in a 7-bit input . |

is there any benefit to use cache if there is read miss for every access? |

How many data bits needed to represent A*B+C, all are 8 bit unsigned |

Complete the C function (body) that uses recursion to determine if the string is a palindrome |

Design a divide by 3 counter. Bonus for 50% duty cycle |

Suppose you have a 4-bit shift register made using D-type flip flops with a positive Clock-to-Q delay and a hold time of 0. Is it possible for this circuit to have hold time violations? Why? |

What would be behavior of a CMOS inverter if the nMOS and pMOS are interchanged? |

Design a circuit that would count 1 every time another counter counts from 0 to 255. One of the counter is working at higher frequency than the other. |

(Unexpected) What the types of caches? |

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