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ASIC Design Engineer Interview Questions


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design a full adder with 2-1 mux

7 Answers

Full Adder can be implemented by two half adder; a half adder can be implemented by a XOR and AND gate. XOR and AND gate can be implemented by 2:1 MUX.

full adder can be got by 2 half adders and one OR gate; one half adder can be got by XOR, AND. Therefore, we need only OR, AND, XOR. All these three gates can be got by using MUX.?

Can be implemented using 8 Muxes.

design a combinational circuit which counts the number of 1s in a 7-bit input .

7 Answers

Design a divide by 3 counter. Bonus for 50% duty cycle

4 Answers

which is hard to fix -- setup violation or hold violation? And why?

4 Answers

Complete the C function (body) that uses recursion to determine if the string is a palindrome

4 Answers

frequency divide by 3 clk circuit

2 Answers

design state machine to test 10110101... how many FF will be used

3 Answers

There are 8 bits inputs ,only use full adder to detect how many logic 1's

2 Answers

is there any benefit to use cache if there is read miss for every access?

4 Answers

how to generate a clock divide by 3

4 Answers
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