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ASIC Engineer Interview Questions

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1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.

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Write some verilog for a 3 to 1 arbiter, with a priority client and 2 clients in a round robin.

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what is the different of Moore and Mealy FSM

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RTL program that covert j-k flip flop to D flip flop

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Logic question to verify the design How would you verify 3 blocks with incorrect label ? suppose one with apple 2 with orange 3 with apple & orange.

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How would you implement a full-adder, both with and without carry-in?

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If I plan to stay for more than 5 years in the company

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Personality is the most important thing.

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Handed out a paper which has several questions on computer architecture. Basic questions such as pipeline structure and asked to draw binary sequence detector

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Which gate would you prefer in a design? Nand or Nor? why?

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