ASIC Intern Interview Questions | Glassdoor

# ASIC Intern Interview Questions

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ASIC intern interview questions shared by candidates

## Top Interview Questions

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May 12, 2012
 there is a disk half painted white and the other half black. There are two sensors and the outputs of these sensors are the only signals available. How will you determine if the disk is rotating clockwise or anti-clockwise? 3 Answers Got an idea however it is valid only if clock can be used additionally to the two sensors. I use clock hours to describe the locations of the 2 sensors. The first sensor will be located at hour 12:00 the second will be located at hour 3:00. Then the first sensor will have to calculate the time it takes for one complete circle by: T=(time change from black to white) * 2 or T=(time change from white to black) * 2 The first sensor deliver signal to the second sensor when there is a change from black to white (or white to black) and the sensor is expecting the change. if the change (from black to white or from white to black) detected at the second sensor T/4 after getting the signal from the first sensor then the disk rounds clockwise else (when it take more then T/4 time) it runs counter clockwise when the second sensor get the signal it start timer to 1/4 Disk - vertically divided, left side White, right side Black, sensors - on upper quadrants horizontal division line of the disk, white sensor in left upper quadrant, black - in the right upper quadrant. 1. No rotation, initial state - White sensor (WS) = HI, Black sensor (BS) = LO 2. Clockwise rotation to 90" : WS =HI, BS changes from LO to HI Truth table (for each 90") WS BS 1 0 1 1 0 1 0 0 1 0 etc WS ==__==__==__==__==__==__==__==__==__==__== BS _==__==__==__==__==__==__==__==__==__==__= 3. Anti-clockwise rotation to - 90" : WS changes from HI to LO, BS=LO Truth table (for each - 90") WS BS 1 0 0 0 0 1 1 1 1 0 etc WS =__==__==__==__==__==__==__==__==__==__ BS __==__==__==__==__==__==__==__==__==__= There is a much simpler solution. Place the sensors about 1/4 circumference apart. Use one FF. Feed one sensor into the clock pin and the other sensor into the D pin. Let's say bottom left sensor is A is is used for the clock. Lets say bottom right sensor (90 degrees apart from A) is connected to the D pin. When the wheel spins, the transition from black to light (0->1) cause the FF to sample the other input. If the D input is 1, the Q will become one and you are rotating CW. If there is a 0->1 transition and the D input is a 0, the Q becomes 0 and we are rotating CCW.

Feb 10, 2014
 How is processor performance affected when the instruction cache hit latency increases? How do you overcome that? 6 Answers latency could increase with increase in cache size, one way to overcome could be to use a multi-level cache, so that L1 cache could be smaller and which decrease s hit latency I assume by 'overcoming' they mean that it cannot be improved by adding levels of cache hierarchy. In that case I think they are looking for a prefetching scheme. Increase in cache latency makes a longer pipeline and increases taken branch penalties. Using branch prediction helps reduce this affect. Show More Responses I don't think prefetching will help reduced "hit latency". Prefetching helps eliminate compulsory misses but to decrease hit latency, it should probably be at the lower levels of abstraction - circuit level. I don't think prefetching will help reduce "hit latency". Prefetching helps eliminate compulsory misses but to decrease hit latency, it should probably be at the lower levels of abstraction - circuit level. 1. Use small, simple cache 2. Split & multi-banked cache organization (instruction cache and data cache) 3. Use virtual indexing and physical tagging rather than virtual address to reduce the time caused by translations. 4. Use way prediction to predict the index 5. Pipeline the write operation, do write the word to block and cache in background

May 12, 2012
 there are 1000 wires in which any number of them can be swapped among themselves. How many bit patterns would you send at the input side to get the correct number of wires that are swapped? 4 Answers 10-bit input (2^10) Any number of wires /2 -1. Might be a more optimal solution i'm not aware of 500 patterns Show More Responses answer = ceiling(log(N))

### ASIC Verification Intern at Ambarella was asked...

Mar 6, 2014
 Design a circuit which outputs a pulse when the input flips. The input is synchronous to a clock. 1 Answer XOR the output of a D flip-flop with its input. Basically, the input is XORed with a delayed input.

### ASIC Engineer Intern at Infinera was asked...

Mar 27, 2014
 How do I connect two designs working at different clock speeds ? 4 Answers Don't know Clock synchronizers. I'm not sure though. pulse synchroniser Show More Responses pulse synchronizer

### ASIC Intern at NVIDIA was asked...

Apr 24, 2012
 Round 1 1- Two to Three Q's on Projects done 2- Designing Q - Consider inputs coming at every clock. I want the output at time = t to give me sum of all nos coming before that time. (Adder is normal adder with latency 1) 3- Designing Q - Consider the same output needed, but adder has a latency of 2. So input is taken at every clock and output is given at every clock. But Input at t=0 is received at output at t=2, input at t=1 is received at output at t=3... 1 Answer 1) rolling adder with input A connected to output of adder, and input B connected to data_in, and a register with CLK and EN inputs for latching the output of the adder at time t (defined by when you want to set the EN signal) 2) same thing essentially, but the adder will have to have a 2-stage pipeline

### ASIC Intern at SanDisk was asked...

Apr 22, 2013
 Digital VLSI questions 1 Answer asic..co.in

Apr 24, 2012