asic verification engineer interview questions shared by candidates
You have 2 pieces of rope, each of which burns from one end to the other in 30 minutes (no matter which end is lit). If different pieces touch, the flame will transfer from one to the other. You cannot assume any rope properties that were not stated. Given only 1 match, can you time 45 minutes?
Take one rope (Rope A), place it down as a circle. Light match and start burning rope A at the tips that are touching. When the rope completely burns out, 15 minutes will have passed (since both ends are burning and being consumed at once). Hold the second rope (Rope B) straight and place one end so that it will immediately catch fire when the two burning points from (Rope A) finally touch and are just about to burn out. Thus 15 minutes on Rope A + 30 minutes on Rope B gives you 45 mins.
How about this: Fold the first rope double so the ends touch. Lay it down and lay the second rope so it touches the fold of the first rope. Light the ends of the first rope. After 15 minutes the second rope should ignite. Once second rope finishes burning it is 45 minutes. Same principle as above, I just don't want to sit there for 15 minutes in order to light the second rope.... :-)
Make a T. Simple
There are two large arrays filled with random 64-bit signed numbers. How do you determine what are the common numbers in the arrays? Give an algorithm that is linear in complexity. You can use unlimited memory.
1st is HR, ask about why Nvidia? expected salary, immigration status, graduation date, etc. 2nd ask about verification methodology (UVM, OVM), system verilog (passing obj as function argument, different type of fork-join, polymorphism etc), use and function of interface in testbench. 3rd ask about arbiter design, setup/hold time, basic logic design, 4rd ask about programming (how to find loops in a linked list), basic C programming and divide by 3 divider. 5th is hiring manager, talk about positions, teams and their products. ask about basic logic design, verilog(syn, asyn, blocking, non-blocking), transistor level design of registers and what could be problem with that design. 6th dude is a funny guy who ask about nothing but just keep talking about the team, what he has done and what he like and don't like about his job, etc. Most difficult: design divide by 3 divider with 50% duty cycle, I don't know how to do that, and the recruiter change the duty cycle to 66%, and I finished it.
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