Circuit Designer Interview Questions | Glassdoor

Circuit Designer Interview Questions

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Why there is a pinch-off during saturation mode of a CMOS device?

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I was quite expecting this question and had been looking for the answer for sometime over the internet. But forgot at the last minute. He lead me to the answer through pn-diode characteristics. And finally explained

How Sense Amplifier works.

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How would you draw the CMOS schematic for a 2-input NAND gate? What would the pull-up and pull-down networks look like? If VDD and VSS are switched, what gate is formed?

2 Answers

How would you size the NMOS and PMOS transistors in an inverter to obtain equal rise and fall times?

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How would you design your own synthesis tool ?

1 Answer

Stack of 2 N transistors connected between VDD and VSS. Calculate the voltage in the mid point if transistors equal in size. Gates both connected to VDD.

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How much experience did I have designing DMMs

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why PMOS is slower than NMOS, questions on computing output of a circuit having complex NMOS pass gate connections etc

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C questions sheet ( 5 questions including questions on binary tree, difference between ++var and var++, sorting question)

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They asked things like if the source of NMOS is open, what is the voltage at the source if the gate and drain at 3 and 5V. If the gate of inverter is connected through a resistor to a output, what is the output voltage? Also things related to ring oscillator. Mostly just digital stuff, nothing analog like others have said.

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