Component design engineer Interview Questions
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Component Design Engineer interview questions shared by candidates
Giving output of a c code
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The answer were three numerals and i got them right in second attempt
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is it correct i.e three numerals ?
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Ravneet the answer were three numbers i don remmeber the exact sequence
How many flops in FSM if you have 4 states
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2 ; if 8 states 3 ; if 16 then 4
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It can be 4 if we are using 1 hot coding
Which is preferred NAND or NOR? And why?
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Nand is Preffered over Nor... The logical effort for a NAND gate is 4/3 and that for a NOR gate is 5/3. The lower the logical effort the better the gate. So a NAND gate is preferred over a NOR gate. If we have two different ways of realizing a boolean function, the type, which has a lower logical effort associated with it, is the better one. Therefore, the NAND gate is better in terms of its ability to drive its output while reducing the load at its input. A NAND gate is preferred over a NOR gate in implementing CMOS logic because, the area occupied by the NOR gate is larger and the associated capacitance is larger for NOR gate, thereby exhibiting more delay for the circuit. If we have NAND logic then the parallel connection of transistor will increase the capacitance linearly increasing the delay. In The series connection of transistors, the delay is quadraticaly proportional to the number of elements in the chain Less
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Nor gate because it's 1 transistor to construct. Nand gate requires 2...slower and more space taken up. Less
how does adding a buffer in the middle of a long wire reduce the delay? CMOS basics: PMOS and NMOS of Inverter operation region under while input varies. how to form a NOT gate using NAND gate.
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A classic interview question, best to just remember this. Tie the two inputs together to form the inverter from the NAND gate. Less
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Delay without buffer = Ru X Cu X L^2 Delay with Buffers = Ru X Cu X Somme (Li ^2) Li = distance between Buffers where L = Somme (Li) It is clear that Somme of Li^2 << L^2 Thus the delay with buffers << Delay w/o Buffer Less
Oscillator from nand gate?
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the basic oscillator is an inverter with its output tied back to its input. For a NAND gate, when all but one input is tied to logic "1", it is fucntionally reduced to an inverter (you can see it from the truth table). So tied the output to one of its input in a feedback mode, and the rest of the inputs to one and you'll get an oscillator Less
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feedback circuit.(Combinational Feedback)
How to fix the hold-time violation after the chip was fabricated?
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Operate at aLower Vdd(not recommended) or operate at a lower temperature...
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can't be fixed....
In addition to technical questions there is alos behavioral questions asked. One example is "tell me about a time when you had to do something different from what the conventional approach suggested".
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This question can get you to be more honest about your style and capabilities, because there is not canned technical answer. Less