Component Design Engineer Interview Questions

Nor gate because it's 1 transistor to construct. Nand gate requires 2...slower and more space taken up.

Nand is Preffered over Nor... The logical effort for a NAND gate is 4/3 and that for a NOR gate is 5/3. The lower the logical effort the better the gate. So a NAND gate is preferred over a NOR gate. If we have two different ways of realizing a boolean function, the type, which has a lower logical effort associated with it, is the better one. Therefore, the NAND gate is better in terms of its ability to drive its output while reducing the load at its input. A NAND gate is preferred over a NOR gate in implementing CMOS logic because, the area occupied by the NOR gate is larger and the associated capacitance is larger for NOR gate, thereby exhibiting more delay for the circuit. If we have NAND logic then the parallel connection of transistor will increase the capacitance linearly increasing the delay. In The series connection of transistors, the delay is quadraticaly proportional to the number of elements in the chain

Apply random stimulus (boundary cases, etc). Add assertions to the design, collect coverage data, etc. Standard functional verification practices.

Blocking :B = A + 1 Non-blocking :B <= A + 1.Blocking gives value before cycle ends non blocking gives value at start of new cycle.

Pipelining, reduce frequency, size the cells, place them closer together, put routing on upper metal layers, skew the clocks

can't be fixed....

Operate at aLower Vdd(not recommended) or operate at a lower temperature...

I don't remember how I answered the circuit part of this question only how it worked.

2 ; if 8 states 3 ; if 16 then 4

It can be 4 if we are using 1 hot coding