# Design Engineer Interview Questions

Design engineer interview questions shared by candidates

## Top Interview Questions

There are 8 bits inputs ,only use full adder to detect how many logic 1's 2 Answersfirst think of how many bits do you need to detect the number of logic 1s in an 8 bit input. highest number will be 8. so you need 4 bits to represent that. how can you compute this value though? the optimal way i think to do this problem is to look at the properties of a full adder. there are 3 inputs (A, B, and Cin) and 2 outputs (S and Cout). You can hook each input of a full adder to a bit value. Therefore, what you end up having is 3 full adders FA0 to compute b0(A) + b1(B) + b2(Cin), FA1 to compute b3(A) + b4(B) + b5(Cin), and FA2 to compute b6(A) + b7(B) + 0 (we dont have a 9th bit). Each FA therefore will produce a 2 bit added sum S1, S2, and S3. Now we need to add S1 and S2 together with 2 FAs, which is pretty straight forward, and get S12. Then we have to add S3 to S12 using 3 FAs because a 3 bit number + a 2 bit number can equal a 4 bit number. We therefore use 7 FAs. Usually, the question is calculate the number of 1s in a 7bit number, which actually reduces the number of FAs to 4. we keep S1 and S2, but don;t need FA3, because we can use bit7 as a Carry in for our computation. Are you not using a total of 8 FAs with your approach here? 3 + 2 + 3 = 8 |

Take a point on a surface. How do you know you're contained inside a box? 3 AnswersThe door plate reads Intel on it. I don't understand the question. Is this an arbitrary mathematical surface? A physical surface of a component? What kind of box are we talking about? check co-ordinate of location versus co-ordinates of box and make sure your location is within the box co-ordinates. |

### ASIC Design Engineer at Broadcom was asked...

how to generate a clock divide by 3 4 AnswersAssuming that input clock is square wave and 50% duty cycle, Method 1: Clk / 3 is equal to Clk / (6/2). this means fist divide by 6 and multiply by 2. dividing by 6( use two DFF(D is tied to Q_b and it is connected to clock of 2nd DFF). multiplying by 2( create some delay and XOR the two signals(the signal after dividing by 6 and its delayed signal), But it's hard to make the output clock have 50% duty cycle due to precise delay control. so alternative method 1 is first multiply by 2 and divide by 6. Method 2. Use 2 edge counters(one for rising edge and the other for falling edge) draw the state machine that goes (back) to toggle state when both counters become 2. Sorry, Method 1 is incorrect. the possible method 1 is to delay the input clock and XOR the input clock and its delayed one(delay doesn't need to be precisely half period of input clock, which is good) then use a single rising edge counter to toggle when it counts 3 rising edges. this is glitch-free Please refer to: http://www.eetimes.com/document.asp?doc_id=1202359 Show More Responses Sorry above is wrong link. correct link: http://vlsiwizard.blogspot.com/2008/01/design-clock-divide-by-3-circuit-with.html |

### ASIC Design Engineer at NVIDIA was asked...

is there any benefit to use cache if there is read miss for every access? 4 Answersno benefit you should probably think a little more about this problem before you just say there's no benefit, thought in most cases I do agree with u. you haven't said anything about write misses, and even though the delay contributed by them isn't as much as a read miss, i'd still mention it as a plus for having a cache, especially in write-back caches where you could potentially have a trace of just writes to locations brought in by your read misses, which means you get n number of cache write hits. Also make sure to mention ways to improve cache hit percentage by either increasing the cache size, changing the associativity of the cache, or by changing the compiler to optimize for the cache type (if we're talkin about an I-cache). Is pattern is such that there would be miss on every access, then there would no benefit of having a cache for both read misses and write misses. If it's a read miss for a block, then there would also be a write miss for that same block. Could you be more specific as to how it would benefit to have cache in such a scenario? Show More Responses The question doesn't say anything about writes. So even if every read is a miss, the cache will help in processor performance by providing write hits. It is very common that we read and update the same variable. For instance a++ or any operation of this sort. So cache is beneficial. |

How can you increase the switching speed of a diode that has already been doped, without changing the geometrical layout of the diode? 2 AnswersYou can use ion implantation doping, to further change the dopant level. You can also irradiate the diode |

What is your salary expectation? 2 AnswersJust tell them you are expecting what fits your qualifications. Never give them an exact figure. Tell them that you don't mind your overall compensation to decrease year after year. Say that you'll be happy with no adjustments for inflation, regular salary cuts, smaller and smaller bonuses, cuts to the company 401K contributions, cuts to the share purchase program, reductions in benefits, no possibilty of any other form of recognition and elimination of all training programs. Explain that you don't mind learning on your own time and that if HP designates you as a mobile worker to save on office costs, then you don't mind paying for your own Internet access, business phone line in your home, and for all travel and supplies that you need to get your job done. Finally, also explain that you don't care if the maximum vacation you can accrue is reduced and are quite happy to schedule the little vacation you have during mandatory company shutdowns. If you need vacation during other times, you are quite willing to forego your salary so that you can spend time with your family. Answering this question in this manner will assure your immediate hire into HP. |

### Software Design Engineer at Amazon was asked...

Given an array of 100 integers where every integer from 1-101 occurs once, except for one. Find the missing integer. 3 Answerssum of number from 1 to n is n(n+1)/2 So Sum from 1 to 101 = (101*102)/2 = 5151 So missing number is 5151 - (sum of all elements in the given array) Let a = XOR of all elements in array and b = XOR of all numbers from 1 to 100. The final result is a XOR b XOR all numbers in the array + till closest power of 2 - 1(in this case 127). Output will be the missing number. i.e. 1 ^ 2 ^ 3 ....... ^ 101 ^ 102...... ^ 127 = missing number |

design state machine to test 10110101... how many FF will be used 3 AnswersFirst design the FSM and get the number of state variables. The number of FFs is the number of state variables (each output depends on the current state (value) of its FF) 4 I think one FF for state vector is enough, other parts are logic gate to decide next state according to input, and logic gate for output according to state vector |

Reverse a sentence but keep the individual words in the same order 2 AnswersComplexity is O(n). Note. string is immutable object so I used stringbuilder for inplace reversal. class ReverseWords { public static void Reverse(ref StringBuilder strInput) { //Reverse the entire sentence Reverse(ref strInput, 0, strInput.Length - 1); //Reverse the words withing reverse sentence int startIndex = 0; int endIndex = 0; while (endIndex < strInput.Length) { if (endIndex == strInput.Length - 1) { Reverse(ref strInput, startIndex, endIndex); startIndex = endIndex + 1; } else if (strInput[endIndex] == ' ') { Reverse(ref strInput, startIndex, endIndex - 1); startIndex = endIndex + 1; } endIndex++; } } private static void Reverse(ref StringBuilder strInput, int startIndex, int endIndex) { for (int i = startIndex; i <= (endIndex + startIndex)/ 2; i++) { char temp = strInput[i]; strInput[i] = strInput[endIndex + startIndex - i]; strInput[endIndex + startIndex - i] = temp; } } } What data structure solution has order 1 look up and is always sorted? |

frequency divide by 3 clk circuit 2 Answersits on the net u can google it out Suppose N=3; duty not 50%: you can use a ring counter, or a Moore FSM; duty 50%, first build a counter 0->2; then generate two enable signals, one active at time n=0, the other active at n=(N+1)/2; apply the two enable signals to two T-FF, the fiest one triggered on posedge, the second one triggered on negedge; the xor the T-FF outputs |

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