Design verification engineer Interview Questions
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Design Verification Engineer interview questions shared by candidates
Create a 8 input AND gate using 3 4:1 muxes
8 Answers↳
Without an enable bit on at least one of the mux's the maximum inputs would be 7. Less
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I don't see it being possible with three standard 4-1 muxes... Using 4, this question is straight forward... The two selects of each mux are your 8 inputs... tie out put of each mux to the (11) case input to the mux. Less
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We need 3 4:1 MUX and a And gate. Are we allowed to use 'and' gate?
You have seven stones and a weighing scale. Six of the stones are equal in weight and one is lighter. How will you figure out which one is lighter ? Minimum tries required to do so ?
5 Answers↳
Needs two weighing at most: 1. Put {1, 2, 3} on LHS and {4, 5, 6} on RHS. 2. If LHS and RHS are equal 7 is the lighter one. else discard heavier of previously weighed group. Now we have a group 3 stones left. Lets call them A, B, C. 3. Put A on LHS and B on RHS. 4. If LHS and RHS are equal C is the lighter one. else lighter or LHS or RHS is the lighter one. Voila! Less
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Two tries. 1st try: 3 : 3, 7th is fake if equal; otherwise, 2nd try: 1:1 picked from the light triple in 1st try. the lighter one is fake if any, the third one fake otherwise. Less
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Trail 1: At random weigh two stones vs. two stones (3 sitting on the side) A: Of the 4 on the scales if one side weighs more then the other then weigh one on each side (since one of them must be heavier) B. If the 2 vs 2 are equal then at random weigh 2 (one on each side) of the three left on the side. If they are the same then the 3rd one that never got weighed is the heaviest. Simple case of process of elimination by grouping (Divide and Test) Less
(Unexpected) What the types of caches?
3 Answers↳
two types: fully associative cache and N-way associative cache
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1. Fully Associative. 2. Direct Mapped. 3. Set Associative
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L1, L2 and L3 caches
Questions on resume, past projects, c coding, verilog coding
2 Answersdifference between non-blocking and blocking assignment
2 Answers2nd phone interview: 1 unit with 9ns delay vs 3 units with delays 2ns, 4ns, 3ns. Which has better throughput and how much?
2 Answers↳
3 units with 2ns, 4ns and 3ns has better throughput. We will have 10 outputs for every 30ns in the second design with 3 units. While we have only 3 outputs for every 30ns. Even though the effective delay of the output in 2nd design is same as the 1st design with single unit, the throughput is more. Less
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3 units with 2ns, 4ns and 3ns has better throughput cuz you can pipeline it.
Randomization in system verilog, UVM basics, caches
2 Answers↳
What did they ask on caches?
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What on randomization? Any other question on systemverilog?
1 is heavier than the other 5 marbles among 6 mables . given a weight to find the heavier one.
2 Answers↳
This should be done in 2 iterations...keep 3 in each hand...higher weight indicates the heavier marble is in that set...now with 3 marbles select 2...if weights are equal then the marble kept aside is the heavier one.. Less
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2 iterations. Take any 4 out of 6 and weigh 2 vs 2. If it is equal, weigh the other 2 as 1vs 1 and find the heaviest. If the 2 v 2 is uneven, take the uneven marbles and weigh them as 1 vs 1 and find the heaviest one. Less
Given integers from 0-100 stored in an array of size 100 how will you find the missing number? Numbers are randomly entered in the array.
2 Answers↳
0-100 have constant addition. add the numbers in the array and subtract it from the constant sum. Less
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Assuming that a number only appears once, find the sum and subtract from the total possible value (1+2+3+....+100) and subtract to find the missing number. But it would be smart to ask if a number can appear multiple times or not since that may increase or decrease the complexity of the problem, but shows that you're really thinking about all the problem parameters. Less