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Design verification engineer Interview Questions


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Create a 8 input AND gate using 3 4:1 muxes

8 Answers

Without an enable bit on at least one of the mux's the maximum inputs would be 7.

Not so. You only need 2 4:1 muxes. Have the output of the first be the select to the second. 8 input and gate.

tie 3 0's to the three inputs of initial 2 4x1 mux, the 3rd input be an actual input, 2 sel be 2 inputs. feed the output of the results of the two muxes as sel to the 3rd mux and tie the last inputs to actual inputs and top two inputs to 0's.

You have seven stones and a weighing scale. Six of the stones are equal in weight and one is lighter. How will you figure out which one is lighter ? Minimum tries required to do so ?

5 Answers

(Unexpected) What the types of caches?

3 Answers

Given integers from 0-100 stored in an array of size 100 how will you find the missing number? Numbers are randomly entered in the array.

2 Answers

1 is heavier than the other 5 marbles among 6 mables . given a weight to find the heavier one.

2 Answers

Rewrite UVM phasing.

2 Answers

1)Should be ready to write some logics (C/Verilog/System Verilog) on the spot . 2)Blocking and Non-Blocking. 3)Fork/join types and applications. 4)Test bench architecture blocks.(asked to write a generalized code to implement gen and bfm).

2 Answers

1) Implement Linked list in hardware 2) LIFO using queues only

2 Answers

How do you prevent the reordering of instructions, and how would you use this as a solution to the above issue?

1 Answer

Can you tell me how do you verify your block ?

1 Answer
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