Design verification engineer interview questions shared by candidates
Create a 8 input AND gate using 3 4:1 muxes
Without an enable bit on at least one of the mux's the maximum inputs would be 7.
Not so. You only need 2 4:1 muxes. Have the output of the first be the select to the second. 8 input and gate.
tie 3 0's to the three inputs of initial 2 4x1 mux, the 3rd input be an actual input, 2 sel be 2 inputs. feed the output of the results of the two muxes as sel to the 3rd mux and tie the last inputs to actual inputs and top two inputs to 0's.
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