Design Verification Engineer Interview Questions | Glassdoor

Design Verification Engineer Interview Questions

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Create a 8 input AND gate using 3 4:1 muxes

7 Answers

Without an enable bit on at least one of the mux's the maximum inputs would be 7.

Not so. You only need 2 4:1 muxes. Have the output of the first be the select to the second. 8 input and gate.

tie 3 0's to the three inputs of initial 2 4x1 mux, the 3rd input be an actual input, 2 sel be 2 inputs. feed the output of the results of the two muxes as sel to the 3rd mux and tie the last inputs to actual inputs and top two inputs to 0's.

You have seven stones and a weighing scale. Six of the stones are equal in weight and one is lighter. How will you figure out which one is lighter ? Minimum tries required to do so ?

5 Answers

1 is heavier than the other 5 marbles among 6 mables . given a weight to find the heavier one.

2 Answers

They mostly concentrate on your resume , computer architecture and digital design basics

1 Answer

Given integers from 0-100 stored in an array of size 100 how will you find the missing number? Numbers are randomly entered in the array.

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How would you verify a write-back 4-way set associative cache using assembly language programming.

1 Answer

design a vending machine from architecture to rtl..

1 Answer

C++ related Questions

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A question about managing branching methodology when dealing with IP cores.

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how to balance the pipeline stage to achieve any specific time period?

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