Design Verification Engineer Interview Questions | Glassdoor

Design Verification Engineer Interview Questions


Design verification engineer interview questions shared by candidates

Top Interview Questions

Sort: RelevancePopular Date

How many quarters would it take to stack end to end from the ground to the top of the empire state building. State your assumptions.

Basics of computer architecture, verification, data structures, rtl logic Telephonic interview was basics of RTL design

What is the difference between using a struct in C and an object in C++?

Discussed C++ Pointers. I was not expecting that topic. Also, Async Fifos, Dynamic Arrays in SV.

Pipelining Hazards?

1 Answer

Do you know anything about RISC Architecture?

1 Answer

For a six-deep FIFO with one (and two clocks), push and pop operations, what specific test cases will you use to verify the design?

can you name all the states of cache?

1 Answer