Design Verification Engineer Interview Questions | Glassdoor

Design Verification Engineer Interview Questions

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Design verification engineer interview questions shared by candidates

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How many quarters would it take to stack end to end from the ground to the top of the empire state building. State your assumptions.

Basics of computer architecture, verification, data structures, rtl logic Telephonic interview was basics of RTL design

What is the difference between using a struct in C and an object in C++?

Discussed C++ Pointers. I was not expecting that topic. Also, Async Fifos, Dynamic Arrays in SV.

Pipelining Hazards?

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Do you know anything about RISC Architecture?

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For a six-deep FIFO with one (and two clocks), push and pop operations, what specific test cases will you use to verify the design?

can you name all the states of cache?

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