Design Verification Engineer Interview Questions | Glassdoor

Design Verification Engineer Interview Questions

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How will you deal with a difficult design engineer?

Main technical topics: logic gates, how to make logic gates out of mosfets, voltage and current limiter question, mosfet fundamentals questions (related to Vgs, V_threshold), and finally a parts list question (what are all the parts you would need to make a DSL gateway?)

(Unexpected) What the types of caches?

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It gets very technical ranging from Electrical fundamentals to RF fundamentals and then they start to dig deep on each aspect. Know your chip caps really well! I was asked questions on smith charts, imedance matching, typical RF receiver/transmitter systems, signal integrity issues, characteristics of RF amps. As far as behavioral questions were concerned - challenges faced in your last project, how did u solve it and what would your ex boss say about you if I asked him for a reference.

What do each of the bits represent in a memory address having a two-way associative cache with size: X words, Y lines, etc.

Write the VHDL or Verilog code for a given state machine diagram.

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