# 401

Digital Design Engineer interview questions shared by candidates

## Top Interview Questions

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Digital Design/Verification Engineer was asked...March 16, 2011

### Create a 8 input AND gate using 3 4:1 muxes

Without an enable bit on at least one of the mux's the maximum inputs would be 7. Less

I don't see it being possible with three standard 4-1 muxes... Using 4, this question is straight forward... The two selects of each mux are your 8 inputs... tie out put of each mux to the (11) case input to the mux. Less

We need 3 4:1 MUX and a And gate. Are we allowed to use 'and' gate?

### How Sense Amplifier works.

Cool question!

Very cool question

I am not from Analog background but my analytical ability lead me through to answer it perfectly. Less

### Given integers from 0-100 stored in an array of size 100 how will you find the missing number? Numbers are randomly entered in the array.

0-100 have constant addition. add the numbers in the array and subtract it from the constant sum. Less

Assuming that a number only appears once, find the sum and subtract from the total possible value (1+2+3+....+100) and subtract to find the missing number. But it would be smart to ask if a number can appear multiple times or not since that may increase or decrease the complexity of the problem, but shows that you're really thinking about all the problem parameters. Less

XOR way is better when any number appears multiple times. XOR of 0 to 100 as signal X, XOR of actual array as signal Y then Xor of X, Y gives missing number. Less

### Cross clock domain synchronizer, 1 bit.

Add one flip-flop on the output of destination register.

There's quite an extended back and forth in actual interviews for questions like this, so nothing quite like real practice. The Prepfully Qualcomm Digital Design Engineer experts have actually worked in this role, so they're able to do an honest-to-God accurate mock, which really puts you through the paces. prepfully.com/practice-interviews Less

### amplifier sizing

key is to recognize the most import mosfets based on various topologies.

It's weird that digital IC design also asked analog question. Or my understanding is wrong If High gain is required, choose larger length, otherwise minimum length for max fT. Less

Yes

FIFO depth of 50

### So tell me about you? Why do you want to work at Netlist?

You got no offer because they prefer to hire their buddy. and only few y of thejob ads actually a real hiring Less

You are lucky you did not pass the interview. It is a terrible hostile working environment if you are not a part of the persian or korean gang. Also, the HR lady has been monitoring this glassdoor like a hawk, because she got not much to do everyday than watching people to make sure they do 8-hour a day like walmart employees. Less

### Verilog question with additional requirements. Design a FSM providing fibonacci sequence with enable and reset. Output should be immediate.

Two registers storing last two numbers in sequence with adding circuit muxed with the enable signal. Combinational output from mux. Answer should be in verilog code. Less

This is actually another way of asking: what is the difference of blocking and non blocking assignment. and the key point in this question is to use the non blocking assignment Less

### What is setup hold time

Setup time is the time the data should be held constant before the arrival of the clock edge. Less

Set Up time is Minimum Amount of time During which Data Signal Should be Stable Before the Clock made a Valid[Low-to-High] Transition. Hold time is the Minimum Amount of time After the Clock Made a Valid Transition During which Data Signal Should Stable. Less