Digital Design Verification Engineer Interview Questions | Glassdoor

# Digital Design Verification Engineer Interview Questions

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Digital design verification engineer interview questions shared by candidates

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### Digital Design/Verification Engineer at SerialTek was asked...

Mar 16, 2011
 Create a 8 input AND gate using 3 4:1 muxes7 AnswersWithout an enable bit on at least one of the mux's the maximum inputs would be 7.Not so. You only need 2 4:1 muxes. Have the output of the first be the select to the second. 8 input and gate.tie 3 0's to the three inputs of initial 2 4x1 mux, the 3rd input be an actual input, 2 sel be 2 inputs. feed the output of the results of the two muxes as sel to the 3rd mux and tie the last inputs to actual inputs and top two inputs to 0's.Show More ResponsesI can only make it 7 bits with that explenation.I don't see it being possible with three standard 4-1 muxes... Using 4, this question is straight forward... The two selects of each mux are your 8 inputs... tie out put of each mux to the (11) case input to the mux.We need 3 4:1 MUX and a And gate. Are we allowed to use 'and' gate?A to H are the 8 inputs. For the first 2 muxes we can have GH as select bits with all their inputs tied to 0. Connect output of these muxes to the first 2 input lines of third mux. Tie the third input to 0. Now we care only about the 4th input line when EH are both 1s. We can derive an expression and connect it to the 4th input line of third mux. job done.

### QCT-Digital Design Verification Engineer at Qualcomm was asked...

Mar 7, 2012
 Given integers from 0-100 stored in an array of size 100 how will you find the missing number? Numbers are randomly entered in the array. 1 Answer0-100 have constant addition. add the numbers in the array and subtract it from the constant sum.

### QCT-Digital Design Verification Engineer at Qualcomm was asked...

Mar 7, 2012
 factorial of a numberBe the first to answer this question

### Digital Design/Verification Engineer at SerialTek was asked...

Mar 16, 2011
 Write the VHDL or Verilog code for a given state machine diagram.Be the first to answer this question

### Digital Design/Verification Engineer at SerialTek was asked...

Mar 16, 2011
 How many quarters would it take to stack end to end from the ground to the top of the empire state building. State your assumptions.Be the first to answer this question
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