# Engineering Design Interview Questions

Engineering design interview questions shared by candidates

## Top Interview Questions

Oscillator from nand gate? 2 Answersfeedback circuit.(Combinational Feedback) the basic oscillator is an inverter with its output tied back to its input. For a NAND gate, when all but one input is tied to logic "1", it is fucntionally reduced to an inverter (you can see it from the truth table). So tied the output to one of its input in a feedback mode, and the rest of the inputs to one and you'll get an oscillator |

CMOS Inverter , how to reduce the drive strength of Minimum size inverter 6 AnswersDrive strength is basically the current carrying capability of a circuit. more the Ids, the lesser the drive strength is. Increase the aspect ration (W/L) of inverter. Usually done in 2:1 ratio (PMOS is slower and sized approx. twice of NMOS) "more the Ids, the lesser the drive strength is" This is exactly opposite of the actual fact...! the first answer is definitely wrong, to decrease the driving capacity, please size down the ratio! Show More Responses It's a minimum size inverter so can't size it down. So may be we can increase the loading capacitance. To reduce a drive-strength at a minimum size inverter, it would be the easiest way to adjust the work-function at gate to adjust the threshold voltage. Use body effect, reverse biasing, this will reduce the drain current. another way can be change the gate input, according to the I-V characteristic |

Roman to Int 2 Answerscreate a dictionary of std. roman values, parse through the roman string and match with the dictionary values -- keep incrementing the output as you iterate and keep truncating the input string as you go through Your answer is incorrect. This is how you should have done it: public static int romanToLatin(String romanNumber) throws Exception { HashMap romanLetters = new HashMap(); romanLetters.put("I", 1); romanLetters.put("V", 5); romanLetters.put("X", 10); romanLetters.put("L", 50); romanLetters.put("C", 100); romanLetters.put("D", 500); romanLetters.put("M", 1000); int stringLength = romanNumber.length() - 1; int result = 0; int last = 0; int sign = 1; int current; for (int i = stringLength; i >= 0; i--) { current = romanLetters.get(romanNumber.subSequence(i, i+1)); if (current > last) { result += current; sign = 1; } else if (current == last) { result += current * sign; } else { result -= current; sign = -1; } last = current; } return result; } |

### Design Engineer at Intel Corporation was asked...

Design a 2:1 MUX using half adders 3 AnswersCan someone post the solution to this question http://images.elektroda.net/70_1274124425.jpg Thanks |

### Software Design Engineer at Amazon was asked...

Given two linked lists A and B, return a new linked list C, where C consists of all elements in A or B that are contained in only A or only B. 2 AnswersHint: hash table! public static void createUniqueListC(List listA, List listB) { Set set = null; List list = null; if (listA != null && listB != null) { set = new LinkedHashSet(); list = listA; int length = listA.size() + listB.size(); for (int i=0; i=listA.size()) { list = listB; i = 0; length = length - listA.size(); } if (!set.add(list.get(i))) { set.remove(list.get(i)); } } Iterator itr = set.iterator(); while (itr.hasNext()) { System.out.println(itr.next()+" "); } } } |

List all possible ways to minimize the power dissipation of an ASIC chip. 2 Answersbreak down this question first into two aspects: Pdyn and Pstat (dynamic power and static power) dynamic power caused by switching activity static power caused by leakage and whatnot -change threshold voltage of transistors. lower threshold voltage, less power dissipation. tradeoff: more susceptible to noise, more unstable, may have to use higher nominal voltage -clock gating: add a simple AND gate (simplest method) to a branch on the clock distribution network to basically turn off clock on flip flops. people use this because clock dissipates a lot of switching power, which is a component of dynamic power. -multi-vdd design: probably most promising method... partition your CPU into different voltage areas so that certain physical areas of the chip can power down or up to different voltages when idle or busy. You need level shifters to implement this... -power gating: goes hand in hand usually with multi-vdd design. Idle areas of the chip can be powered down completely sometimes. You need isolation gates for this... -dynamic frequency-voltage scaling (voltage regulation): think of overclocking your computer. for example, if you overclock your CPU by 10%, you may need 13% increase in your VDD. Similarly, maybe an idle portion of the CPU only needs an operating frequency of 1Ghz as opposed to 2.6GHz. In asic design, usually this highly analog component can be black boxed as hard IP and inserted into ur asic design. Means to implement these power dissipation techniques: theres been huge leaps done in industry recently (past decade) by Intel and other asic design companies as well as IEEE to standardize multi voltage design and power gating. look at UPF and CPF languages. UPF is standardized by IEEE and basically lets desginers write a separate input file called a power intent file that goes along with RTL into synthesis, verification, and layout tools. what this means is partitioning different logical and physical areas of the asic chip by power supply. for example, maybe your FPC needs 2.5V but your clock management unit needs 3V. To clarify, if you use power gating =/= clock gating. if you use power gating on a voltage area, you are gating the power supplies into that block... think Vdd and Vss, ie you are also turning power off to the that subnetwork of clocks. if you are clock gating, you are gating just the clock, but the flop is still connected to power. this means that if you use power gating, you may need to implement retention flops if you have any flip flops in your power gated block. in summary, the effect of clock gating usually is a subset of the effects of power gating. that's why power gating is much more effective. |

1 is heavier than the other 5 marbles among 6 mables . given a weight to find the heavier one. 2 AnswersThis should be done in 2 iterations...keep 3 in each hand...higher weight indicates the heavier marble is in that set...now with 3 marbles select 2...if weights are equal then the marble kept aside is the heavier one.. 2 iterations. Take any 4 out of 6 and weigh 2 vs 2. If it is equal, weigh the other 2 as 1vs 1 and find the heaviest. If the 2 v 2 is uneven, take the uneven marbles and weigh them as 1 vs 1 and find the heaviest one. |

There are 8 bits inputs ,only use full adder to detect how many logic 1's 2 Answersfirst think of how many bits do you need to detect the number of logic 1s in an 8 bit input. highest number will be 8. so you need 4 bits to represent that. how can you compute this value though? the optimal way i think to do this problem is to look at the properties of a full adder. there are 3 inputs (A, B, and Cin) and 2 outputs (S and Cout). You can hook each input of a full adder to a bit value. Therefore, what you end up having is 3 full adders FA0 to compute b0(A) + b1(B) + b2(Cin), FA1 to compute b3(A) + b4(B) + b5(Cin), and FA2 to compute b6(A) + b7(B) + 0 (we dont have a 9th bit). Each FA therefore will produce a 2 bit added sum S1, S2, and S3. Now we need to add S1 and S2 together with 2 FAs, which is pretty straight forward, and get S12. Then we have to add S3 to S12 using 3 FAs because a 3 bit number + a 2 bit number can equal a 4 bit number. We therefore use 7 FAs. Usually, the question is calculate the number of 1s in a 7bit number, which actually reduces the number of FAs to 4. we keep S1 and S2, but don;t need FA3, because we can use bit7 as a Carry in for our computation. Are you not using a total of 8 FAs with your approach here? 3 + 2 + 3 = 8 |

Take a point on a surface. How do you know you're contained inside a box? 3 AnswersThe door plate reads Intel on it. I don't understand the question. Is this an arbitrary mathematical surface? A physical surface of a component? What kind of box are we talking about? check co-ordinate of location versus co-ordinates of box and make sure your location is within the box co-ordinates. |

### ASIC Design Engineer at Broadcom was asked...

how to generate a clock divide by 3 4 AnswersAssuming that input clock is square wave and 50% duty cycle, Method 1: Clk / 3 is equal to Clk / (6/2). this means fist divide by 6 and multiply by 2. dividing by 6( use two DFF(D is tied to Q_b and it is connected to clock of 2nd DFF). multiplying by 2( create some delay and XOR the two signals(the signal after dividing by 6 and its delayed signal), But it's hard to make the output clock have 50% duty cycle due to precise delay control. so alternative method 1 is first multiply by 2 and divide by 6. Method 2. Use 2 edge counters(one for rising edge and the other for falling edge) draw the state machine that goes (back) to toggle state when both counters become 2. Sorry, Method 1 is incorrect. the possible method 1 is to delay the input clock and XOR the input clock and its delayed one(delay doesn't need to be precisely half period of input clock, which is good) then use a single rising edge counter to toggle when it counts 3 rising edges. this is glitch-free Please refer to: http://www.eetimes.com/document.asp?doc_id=1202359 Show More Responses Sorry above is wrong link. correct link: http://vlsiwizard.blogspot.com/2008/01/design-clock-divide-by-3-circuit-with.html |

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