Fpga engineer Interview Questions | Glassdoor

Fpga engineer Interview Questions

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FPGA designers that use Verilog are typically not good at using object oriented languages like System Verilog.

2 Answers

I was taken aback by the statement, especially since I am an FPGA designer that uses both Verilog and System Verilog at my current job. To respond to the statement, I simply assured the interviewer that I was more than capable of using both HDL languages at a near-expert level as demonstrated by my background.

The interviewer to be clueless about HDL...

So tell me about you? Why do you want to work at Netlist?

2 Answers

How do you pass timestamp register from one clock domain to another.

2 Answers

If I called this guy (so and so that MD knew from previous job), what would he say about you ?

1 Answer

Verilog function to find first index of 1 in a bit vector. A joke.

1 Answer

Code a 9-pixel averaging filter in Verilog

1 Answer

ALP questions - what was your biggest technical mistake, have you had to disagree with your boss, etc.

1 Answer

What is the mean time between failures for a flip-flop that has asynchronous data input.

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What are blocking and non-blocking statements in Verilog?

1 Answer

mostly about previous experience and some technical questions like race condition and timing analysis

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