fpga engineer interview questions shared by candidates
FPGA designers that use Verilog are typically not good at using object oriented languages like System Verilog.
I was taken aback by the statement, especially since I am an FPGA designer that uses both Verilog and System Verilog at my current job. To respond to the statement, I simply assured the interviewer that I was more than capable of using both HDL languages at a near-expert level as demonstrated by my background.
The interviewer to be clueless about HDL...
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