Fpga engineer Interview Questions
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Fpga Engineer interview questions shared by candidates
In a synthesis process, when you find a problematic route, how can you solve it?
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Depends on the error. "Routes" are usually an issue during Place & Route. Errors in synthesis are usually due to bad RTL code. Check for synthesis warnings using linting tools if you can find it visually. Check the post synthesis schematic to view how the synthesis tool interpreted your code. Less
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Synthesis reports will report warnings and errors. See if there’s anything in the error report that points to an area of code related to the bad “route”. Run the RTL thru a linting program also. Use the post synthesis schematic view of the RTL in question and see if that’s what you intended. Less
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For what I know, one can add more pipeline stages or check logic for overhead. As I told him, my experience is not in synthesis. Less
FPGA designers that use Verilog are typically not good at using object oriented languages like System Verilog.
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The interviewer to be clueless about HDL...
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I was taken aback by the statement, especially since I am an FPGA designer that uses both Verilog and System Verilog at my current job. To respond to the statement, I simply assured the interviewer that I was more than capable of using both HDL languages at a near-expert level as demonstrated by my background. Less
So tell me about you? Why do you want to work at Netlist?
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You got no offer because they prefer to hire their buddy. and only few y of thejob ads actually a real hiring Less
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You are lucky you did not pass the interview. It is a terrible hostile working environment if you are not a part of the persian or korean gang. Also, the HR lady has been monitoring this glassdoor like a hawk, because she got not much to do everyday than watching people to make sure they do 8-hour a day like walmart employees. Less
How to use stack and heap in C programming language?
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Not difficult but quite confused. My first thought was how to implement stack or heap...Then I think maybe there are some std libraries. The stack is used for functional calls and heap is for dynamic allocation. Details is here http://stackoverflow.com/questions/79923/what-and-where-are-the-stack-and-heap. Less
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If i applied for a hardware job and they asked my a software question, I would walk out. Less
they asked about projects I involved and my roles and responsibilities. the tools used and debugging using tools. real-time issues faced and their solution.
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they just find you are really worthful or not.
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The key in these questions is to cover the fundamentals, and be ready for the back-and-forth with the interviewer. Might be worth doing a mock interview with one of the Xilinx or ex-Xilinx FPGA Design Engineer experts on Prepfully? They give real-world practice and guidance, which is pretty helpful. prepfully.com/practice-interviews Less
How do you pass timestamp register from one clock domain to another.
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Typically timestamps are sampled at sop of packets, so 2 samples can have multiple bits change. Use data mux synchronizer if the gap between two samples is larger than 2/3 synchronizer delay. Less
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Assuming the time stamp increments, gray-encode it and pass it through dual flip-flop synchronizers. Less
Describe setup and hold violation with waveforms
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Setup - The time required to setup an incoming waveform before the clock edge. Hold - The time required by the waveform to hold its value after the clock edge. What does this mean? We all know that the consequence of both of the above said violations is METASTABILITY. How metastability occurs? We all know that any logic bit (0/1/X) have different ranges of voltages. Suppose the input signal obey the voltage standard in which the following is true: 1. Logic 0 is applicable when the input signal is in the range of 0 to 0.8 V 2. Logic X is applicable when the input signal is in the range of 0.8 to 2 V 3. Logic 1 is applicable when the input signal is in the range of 2 to 3.3 V Now if I sampled the input signal between 0 to 0.8 V, the circuit will interpret it as Logic 0. Similarly, if I sampled the input signal between 2 to 3.3 V, the circuit will interpret it as Logic1. But what if, mistakenly, I sampled the signal between 0.8 to 2 V: the circuit will interpret it as neither 0 nor 1. So it is declared as X. This is metastability. Since we know that all the signals are analog in nature. It means, there is the transition in the behavior of the signal from logic 0 to logic1. Or, in other words, there will be finite non-zero time to reach from logic 0 to logic 1. Hence, in order to sample logic 1 on the input signal, the signal has to pass sufficient time to settle to at least 2V. This time is called setup time. If I sample the signal before the instant when it reaches 2V, the circuit interpret the signal as logic X and will eventually go into metastability due to setup time violation. Similar logic holds for hold time violation. If the input signal changes its state before a particular period after the clock edge, the circuit will go into hold time violation. This transient time to reach the signal from logic 0 to logic 1 depends on the stray capacitance of the load connected ahead. If the stray capacitance is more, the transient time is more. If the stray capacitance is less, the transient time is less. This stray capacitance depends on the gate management inside the flipflop (load connected). In other words, the transient time depends on the flip flop (load). Hence, the setup time is the characteristic of the flipflop connected in the path and we design our circuit based on the flipflops inside the FPGA. Less
1. design a module => y=5x with n bit input 2. design a module => for a serial input detect when the number is divided by 5 without any reminder
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1. 2n+1 left shift then add 1 2. FSM that is based on answer 1