Ic design engineer Interview Questions
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Ic Design Engineer interview questions shared by candidates
How to make sure the 2-stage opamp is stable? How does the compensation work?
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Using Miller compensation. A compensation capacitor across the 2nd stage to create pole splitting. A series resistor to the cap might be needed to solve the rhp zero problem Less
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Using compensation capacitor, which makes the low frequency pole's frequency become lower and high frequency pole's frequency higher, so OPmap is more stable. Less
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Using compensation network including capacitor and resistor and monitoring the phase margin and gain margin as well. Less
1) Given an NMOS, 5V on Drain, 4V on Gate, what is voltage on source? 2) What happens when using a NMOS to pull up and/or a PMOS to pull down? 3) Given a rotating disk that's 1/4 black and 3/4 white, assume you have two sensors 90 degrees apart. How can you determine the direction the disk is rotating (clockwise vs counterclockwise) with some cmos circuit?
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a simple phase error detector (lead /lag) would work (frequency not needed), e.g. cw gives phase error 90 degrees, ccw gives 270 degrees, with b/w sensors analogous to rise and fall of a clock edges. Less
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2) what if you have a leakage
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2) You get a Vt drop on the output.
Just some C++basics since I had not prepared C++ at all. Arrays and pass by reference and value.
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overall was good interview experience
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There's a lot of elements to typically cover in these questions, clarifications, scoping, making sure you're answering the actual question the interviewer is looking for you to answer, etc. Could be worth doing a mock interview with one of the Prepfully Broadcom IC Design Engineer experts... they've worked in the role so they clearly know how to get through the interview. prepfully.com/practice-interviews Less
how to bias a cascode current mirror? how you would layout it?
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- Biasing the gate of the cascode devices with a ratio of 1/5 or 1/6 (W/L) to ensure the lower device stay in saturation. If we have a ratio lower than 1/6, then we are decreasing the minimum Vo for the cascode device. - The 1/5 (W/L) device while having a long channel, its better to layout it with 5 (W/L) transistors connected in series. Why? to decrease the variation of Vt of long channel transistors Less
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Mirroring transistors has to be matched and interdigitized to reduce 2nd order effects. Using multiplier matches the transistor better. Less
Gave me a STA report and asked me to fix violations
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Through questions like this, interviewers are mostly trying to test your skillset (and its relevance to the role) as robustly as possible, so be prepared for multiple offshoots and followups. It could be a useful exercise to do mocks with friends or colleagues in Xilinx to get a real sense of what the interview is actually like. Alternatively Prepfully has a ton of Xilinx IC Design Engineer experts who provide mock interviews for a pretty reasonable amount. prepfully.com/practice-interviews Less
Why would people come if I try to hire them into Maxlinear.
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Because they have followed before.