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Integration Engineer Interview Questions

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How does a substrate bias (a.k.a. back-gate bias) on a MOS transistor affect Vt?

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A back-gate bias increases the magnitude of Vt. The mechanism is an increase in the depletion width of the induced p-n junction under the gate. This uncovers more fixed charge in the channel region. (The mobile charge gets "pulled" to the substrate contact.) Since the uncovered fixed charge has the same sign as the channel inversion charge, not as much channel inversion charge is needed to balance the charge on the gate. As a result, some of the inversion charge flows out the source terminal, so the channel isn't as inverted as it was prior to applying the substrate bias. Therefore, the gate voltage needs to increase in magnitude to restore the previous level of channel inversion.

Generally speaking, it is the so called body effect. For NMOS, with the decrease of VB, VTH increases.

All sorts of questions. One interviewer has a full list of 20+ questions to blast thur. Didn't seem to care how and what I've done from my past job experience.

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RF modeling Experience

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Layout Dependent Effects in a Transistor

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common questions

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I was asked if I knew what "WoW" was, meaning "windows on windows 64-bit" which is what allows 32-bit applications to work in a 64-bit environment.

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We had an issue with people installing batteries upside down. How would you prevent this from happening?

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Fairly typical question about the most difficult problem I had encountered and how I went about solving it.

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Lots (a whole lot) of technical questions. Know your equations, concepts, etc. Was asked a couple questions like: "(*such and such event*) just happened, how do you fix this within the next 30 min so that we can launch? Would you do anything differently if given more time?"

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SQL Logic test on paper. It was fun but challenging.

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