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Intern - IC Design Interview Questions


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design AND from Mux

2 Answers

2to1 Mux output is 0 if select(B)=0, and A if select(B)=1, it represents A AND B.

Wire input1 to 0 and input2 to A and select to B.

What type of capacitor does PLL tap?

1 Answer

Draw an SR-latch

1 Answer

What is the Miller Effect?

1 Answer

last round of interview was out of the blue.. was asked many questions about CPU Design and placement..

None - they were just testing my ability to think on my feet

In the final round , I was asked some logic puzzle which was unexpected, I took some time but finally solved it.

How to design a counter to count the rising/falling edge of a signals; how to use RTL to realize I2C EEPROM protocol.

Technical questions on cross clock domain synchronization, metaflops, slightly complex verilog questions, setup and hold time, basic questions on C++.

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