Design Engineer Interview Questions in Los Angeles, CA | Glassdoor

# Design Engineer Interview Questions in Los Angeles, CA

184

Design engineer interview questions shared by candidates

## Top Interview Questions

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### ASIC Design Engineer at Marvell Semiconductor was asked...

Sep 7, 2011
 design state machine to test 10110101... how many FF will be used3 AnswersFirst design the FSM and get the number of state variables. The number of FFs is the number of state variables (each output depends on the current state (value) of its FF)4I think one FF for state vector is enough, other parts are logic gate to decide next state according to input, and logic gate for output according to state vector

Oct 5, 2011
 how to generate a clock divide by 34 AnswersAssuming that input clock is square wave and 50% duty cycle, Method 1: Clk / 3 is equal to Clk / (6/2). this means fist divide by 6 and multiply by 2. dividing by 6( use two DFF(D is tied to Q_b and it is connected to clock of 2nd DFF). multiplying by 2( create some delay and XOR the two signals(the signal after dividing by 6 and its delayed signal), But it's hard to make the output clock have 50% duty cycle due to precise delay control. so alternative method 1 is first multiply by 2 and divide by 6. Method 2. Use 2 edge counters(one for rising edge and the other for falling edge) draw the state machine that goes (back) to toggle state when both counters become 2.Sorry, Method 1 is incorrect. the possible method 1 is to delay the input clock and XOR the input clock and its delayed one(delay doesn't need to be precisely half period of input clock, which is good) then use a single rising edge counter to toggle when it counts 3 rising edges. this is glitch-freePlease refer to: http://www.eetimes.com/document.asp?doc_id=1202359Show More ResponsesSorry above is wrong link. correct link: http://vlsiwizard.blogspot.com/2008/01/design-clock-divide-by-3-circuit-with.html

### Product Designer, Engineering at Remo was asked...

Sep 7, 2011
 Suppose a theater company calls and requests that a drum be custom fitted to appear inside a large barrel and sounding a certain way. Describe the design process you would use to accomplish this.1 AnswerEssentially the question is getting at how well you can translate often vague customer requirements into engineering specifications, keeping in mind the existing parts catalog, materials, cost, etc.

Sep 15, 2015

### Design Engineer at Gogo was asked...

Oct 6, 2014
 What would you be best performing at?1 AnswerAs a 20 year generalist engineer, this is a difficult answer. Find an answer that best suits the position.

Jul 26, 2012
 I was asked a puzzle1 AnswerInterview was pretty straight forward and easy

### Hardware Design Engineer at simplehuman was asked...

Jan 8, 2013
 What is the difference between Gerber formats RS-274 and RS-274X?1 AnswerAperture definitions are included in the ASCII files in RS-274X.

### Embedded Design Engineer at Empower RF Systems was asked...

Oct 4, 2015
 For Embedded RTOS and uController&amp;#039;s Single Task, Comparing performance.1 AnsweruContoller task is little faster than RTOS response time. Because uController system is optimized for peripherals like uart, spi, i2c.

### Design Engineer at ITT was asked...

Aug 24, 2012
 Technical questions.1 AnswerBe confident with you response and be honest if you don't know, but say that you learn fast.

### Senior RFIC Design Engineer at Skyworks Solutions was asked...

Apr 4, 2019
 Smith charts for LNA matching + LNA design (gain/NF/IIP3 optimization) + Inductor design + RF Switch design + OpAmps/LDOs + Bandgaps 1 Answerall text book questions. Make sure to review LNA design and basic analog concepts
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