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Device Engineer Interview Questions in Milpitas, CA

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What is gate induced barrier lowering effect?

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I think it should be "Drain induced barrier lowering" which is related to the reduction in the threshold voltage of the transistor due to the large depletion region created by the Drain potential. "

It also can be confused with "Gate-Induced Drain Leakage", wich is different from DIBL. Due to the high e-field on Gate-Drain interface during off-state (with D-S bias), e-h pairs can be formed through tunneling. Each of them goes to the drain or channel and induces drain current. Please see : http://nanohub.org/resources/5690/download/2008.10.28-ece612-l16.pdf

Describe about NAND and NOR memory structure.

They asked me my Ph.D works and previous professional work experience and knowledge. Mostly easy, but sharp questions. The hiring manager told me he already knew about me through the phone call interview as well as resume, so it's my tun to ask him about everything. One interviewer grilled me with tricky questions about weird transistor structures. The manager and a technical VP were very friendly and nice guys.

problems based on capacitors, NAND flash device structures (program/erase/leakage etc)