Physical design engineer interview questions shared by candidates
You are give two flip-flops and there's an combination logic in between, the two flip-flops are driven by the same clock. You are provided with parameters of T_reg, T_logicmax, T_logicmin, T_setup, T_hold, etc. How to determine the cycle time and hold time of this circuits.
a very basic sequential logic interview question
T_reg + T_logicmax + T_setup = T_hold - T_reg (hold check)
Draw a two-put NAND gate and size it, assuming the ratio of PMOS/NMOS is 2 in inverter. Then suppose two input are A and B for NMOS and PMOS. A is close to output and B is close to ground, input A change from 0 to 1 at t=t1, input B change from 0 to 1 at t =t1 (t1 > t0). Describe how the output change. Then input B changes from 0 to 1 first then input A changes from 0 to 1. Describe how the output changes. Are there any differences between these two scenarios?
why did you quit your job ? i quit my job and was my personal decision . interviewer was too curious to know why what etc. Seemed he was more upset more than me and worried i quit my job after 10 years. I told him i just needed a change and i already have a offer. It did not make him happy still.
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