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Physical design engineer Interview Questions


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CMOS Inverter , how to reduce the drive strength of Minimum size inverter

8 Answers

Drive strength is basically the current carrying capability of a circuit. more the Ids, the lesser the drive strength is. Increase the aspect ration (W/L) of inverter. Usually done in 2:1 ratio (PMOS is slower and sized approx. twice of NMOS)

"more the Ids, the lesser the drive strength is" This is exactly opposite of the actual fact...!

the first answer is definitely wrong, to decrease the driving capacity, please size down the ratio!

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Explain a scenario where hold violation can be fixed by lowering frequency.

4 Answers

Draw a two-put NAND gate and size it, assuming the ratio of PMOS/NMOS is 2 in inverter. Then suppose two input are A and B for NMOS and PMOS. A is close to output and B is close to ground, input A change from 0 to 1 at t=t1, input B change from 0 to 1 at t =t1 (t1 > t0). Describe how the output change. Then input B changes from 0 to 1 first then input A changes from 0 to 1. Describe how the output changes. Are there any differences between these two scenarios?

4 Answers

What's power gating and clock gating. Briefly explain setup time and hold time violation. Briefly describe what is physical design. Sequence Detector. And some questions about my project.

5 Answers

talk about the clock distribution

7 Answers

You are provided with one XOR gate, one OR gate and one NOR gate. Please build a NAND gate.

5 Answers

You are give two flip-flops and there's an combination logic in between, the two flip-flops are driven by the same clock. You are provided with parameters of T_reg, T_logicmax, T_logicmin, T_setup, T_hold, etc. How to determine the cycle time and hold time of this circuits.

4 Answers

how do you Implement blocks using IC Design Compiler?

4 Answers

Your work experience in latest technology, design process, tools used, issues seen and how they were resolved

5 Answers

How to modify a two-input NAND gate to an inverter?

4 Answers
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