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Physical Design Engineer interview questions shared by candidates

## Top Interview Questions

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Physical Design Engineer was asked...April 20, 2011

### CMOS Inverter , how to reduce the drive strength of Minimum size inverter

"more the Ids, the lesser the drive strength is" This is exactly opposite of the actual fact...! Less

Use body effect, reverse biasing, this will reduce the drain current. another way can be change the gate input, according to the I-V characteristic Less

the first answer is definitely wrong, to decrease the driving capacity, please size down the ratio! Less

### Explain a scenario where hold violation can be fixed by lowering frequency.

It won’t affect for the full cycle path. But it improves hold timing for half cycle paths Less

I tried to look into it, I dont see any scenario in which hold would be fixed by lowering frequency, unless any of the derates are functional to the frequency. Less

Negedge =&gt; posedge or posedge =&gt; negedge path. Basically, half cycle sequential paths. Less

### Draw a two-put NAND gate and size it, assuming the ratio of PMOS/NMOS is 2 in inverter. Then suppose two input are A and B for NMOS and PMOS. A is close to output and B is close to ground, input A change from 0 to 1 at t=t1, input B change from 0 to 1 at t =t1 (t1 &gt; t0). Describe how the output change. Then input B changes from 0 to 1 first then input A changes from 0 to 1. Describe how the output changes. Are there any differences between these two scenarios?

Case 1: Lets say A is a stable '1' , the intermediate node between the A &amp; B transistor will be charged to VDD-Vt. When B changes from '0' to '1', it takes time for that node to discharge. Case 2: Lets say B is a stable '1', the intermediate node is already discharged. When A changes from '0' to '1',the output will switch faster since the intermediate node is already discharged. Less

input pattern affect delays, parasitic capacitance effect

for the second scenerio, there will be high leakage current compared to the first scenario, as A will be off for more time while having Vds = Vdd which makes leakage high, it is not the same situation for the first scenario. Less

### What's power gating and clock gating. Briefly explain setup time and hold time violation. Briefly describe what is physical design. Sequence Detector. And some questions about my project.

Power Gating:In a processor chip, certain areas of the chip will be idle and will be activated only for certain operations. But these areas(cmos) are still provided with power for biasing. The power gating limits this unnecessary power being wasted by shutting down power for that area and resuming whenever needed. Clock Gating: clock gating limits the clock from being given to every register or flops in the processor.In clock gating the gated areas will still be provided with bias power. Less

Power Gating:In a processor chip, certain areas of the chip will be idle and will be activated only for certain operations. But these areas(cmos) are still provided with power for biasing. The power gating limits this unnecessary power being wasted by shutting down power for that area and resuming whenever needed. Clock Gating: clock gating limits the clock from being given to every register or flops in the processor.In clock gating the gated areas will still be provided with bias power. Less

Power Gating:In a processor chip, certain areas of the chip will be idle and will be activated only for certain operations. But these areas(cmos) are still provided with power for biasing. The power gating limits this unnecessary power being wasted by shutting down power for that area and resuming whenever needed. Clock Gating: clock gating limits the clock from being given to every register or flops in the processor.In clock gating the gated areas will still be provided with bias power. Less

### build the func f=(ab+c`)` using min mux 2:1

(ab+c`)`=(ab)`c let`s say that mux lets bit z choose from x or y so the output is zy+z`x first mux a choose from 0,b to get ab then ab choose from 1,0 to get (ab)` then c choose from 0,(ab)` to get (ab)`c Less

Both of these answers are confusing , can someone post a clear answer with picture and diagram neatly. Less

This is the correct answer: PREFERENCE # DATE TIME (PACIFIC TIME) F = 2:1 mux(.0(0), .1(2:1 mux(.0(1), .1(B`), .sel(A))], .sel(C)) It must be B bar not B Less

### talk about the clock distribution

I tried rooftop slushie mentioned above and it was pretty helpful. I recommend it. Less

why: clock branches not toggle at same time because of route difference from clock source what to do: scan the clock arriving time and align the clock with buffers Less

### You are provided with one XOR gate, one OR gate and one NOR gate. Please build a NAND gate.

Use the NOR and XOR gates as inverters and hook them up to the inputs of the OR gate. This is the De-Morgan equivalent of a NAND gate. Less

Convert the xor into inverter by connecting one of its i/p to logic 1

use truth table and see the pattern

### You are give two flip-flops and there's an combination logic in between, the two flip-flops are driven by the same clock. You are provided with parameters of T_reg, T_logicmax, T_logicmin, T_setup, T_hold, etc. How to determine the cycle time and hold time of this circuits.

Setup: T_reg+T_logicmax T_hold You can add the uncertainties etc as needed

a very basic sequential logic interview question

T_reg + T_logicmax + T_setup = T_hold - T_reg (hold check)

### Your work experience in latest technology, design process, tools used, issues seen and how they were resolved

Went over the latest design issues we have been seeing how we were addressing them with design fixes and tool fixes and out of the box solutions Less

I went through some design program such as Plc ,scada , autocad and c++ . I got experience through those design program project for my training course with UTM University. Which mean I got some experience in using those design program Less

Another great piece of content from Rooftop Slushie: bit.ly/faang100

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