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Physical Design Engineer Interview Questions

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You are provided with one XOR gate, one OR gate and one NOR gate. Please build a NAND gate.

4 Answers

use truth table and see the pattern

Use the NOR and XOR gates as inverters and hook them up to the inputs of the OR gate. This is the De-Morgan equivalent of a NAND gate.

Convert the xor into inverter by connecting one of its i/p to logic 1

You are give two flip-flops and there's an combination logic in between, the two flip-flops are driven by the same clock. You are provided with parameters of T_reg, T_logicmax, T_logicmin, T_setup, T_hold, etc. How to determine the cycle time and hold time of this circuits.

3 Answers

CMOS Inverter , how to reduce the drive strength of Minimum size inverter

7 Answers

Why do you want to relocate from India to US

1 Answer

DCG related, how to fix timing? Verilog RTL case x, case z, DFF, Dlatch Perl scripting TCL scripting in PT ICC Design patitioning

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Draw a two-put NAND gate and size it, assuming the ratio of PMOS/NMOS is 2 in inverter. Then suppose two input are A and B for NMOS and PMOS. A is close to output and B is close to ground, input A change from 0 to 1 at t=t1, input B change from 0 to 1 at t =t1 (t1 > t0). Describe how the output change. Then input B changes from 0 to 1 first then input A changes from 0 to 1. Describe how the output changes. Are there any differences between these two scenarios?

3 Answers

Draw an inverter. Then switch the position of NMOS and PMOS. Describe the circuit.

3 Answers

How to modify a two-input NAND gate to an inverter?

3 Answers

Tell me what you enjoy about working in HR? Which part of HR do you like best?

1 Answer

What's power gating and clock gating. Briefly explain setup time and hold time violation. Briefly describe what is physical design. Sequence Detector. And some questions about my project.

5 Answers
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