Physical Design Engineer Interview Questions | Glassdoor

Physical Design Engineer Interview Questions

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You are give two flip-flops and there's an combination logic in between, the two flip-flops are driven by the same clock. You are provided with parameters of T_reg, T_logicmax, T_logicmin, T_setup, T_hold, etc. How to determine the cycle time and hold time of this circuits.

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a very basic sequential logic interview question

T_reg + T_logicmax + T_setup = T_hold - T_reg (hold check)

You are provided with one XOR gate, one OR gate and one NOR gate. Please build a NAND gate.

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CMOS Inverter , how to reduce the drive strength of Minimum size inverter

6 Answers

How to modify a two-input NAND gate to an inverter?

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Draw an inverter. Then switch the position of NMOS and PMOS. Describe the circuit.

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Draw a two-put NAND gate and size it, assuming the ratio of PMOS/NMOS is 2 in inverter. Then suppose two input are A and B for NMOS and PMOS. A is close to output and B is close to ground, input A change from 0 to 1 at t=t1, input B change from 0 to 1 at t =t1 (t1 > t0). Describe how the output change. Then input B changes from 0 to 1 first then input A changes from 0 to 1. Describe how the output changes. Are there any differences between these two scenarios?

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VLSI lower power design techniques, FSM sequence detection, transistor layout, combinational circuit design, timing (setup, hold time), floorplanning, noise, crosstalk

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Difference Between SRAM and DRAM

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why did you quit your job ? i quit my job and was my personal decision . interviewer was too curious to know why what etc. Seemed he was more upset more than me and worried i quit my job after 10 years. I told him i just needed a change and i already have a offer. It did not make him happy still.

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What's power gating and clock gating. Briefly explain setup time and hold time violation. Briefly describe what is physical design. Sequence Detector. And some questions about my project.

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