Project electrical engineer interview questions shared by candidates
Q2: A pnp transistor with its base connected to a voltage source, the V source is connected to a +10V source. The emitter of the transistor is connected to a resistance, and then to the same +10V source. The collector side is connected to a capacitor, which is not charged at t=0-. Given the graph of Vsource = 10 V stepping up at t = 0 to further, draw the graph of Vout. Vout is between the point of collector and capacitor.
ANS: Vout should be constantly -10V until t=0, and will hit V=0 V linearly from V=-10 V after t=0.
Hi, Can you explain why it linearly increases? Are you assuming that Collector is tied to -10V? The pnp transistor is completely cutoff for the given biasing. The only way the capacitor is going to charge is through leakage currents. It is very slow and takes a lot of time. Please advise me if my analysis is correct.
I just made it back from Lutron's HQ and I was asked for the same question. My first approach will be identifying a PNP BJT, and elaborating all 4 BJT operating regions. Before t = 0, since q = 0, by using Q = CV, we can tell that the voltage across the capacitor is 0. Hence, Vo = -10V before t = 0. Recall the capacitor's current equation: I = C*(dv/dt), we can solve for the slope of changing voltage -> dv/dt = I/C. Here, I is simply the BJT's collector current, which can be found by looking at the BJT's emitter current. Given that the (beta) parameter is infinite, we see the base current to be 0. Now, at this point, we need to look for I_E. Since the R is given to be 9.3k, and VEE = 10V, it is natural to assume V_EB = 0.7V, and thus the voltage across R = 9.3V. Therefore, I_E = 9.3/9300 = 1mA. Voila, we now values for all currents: I_E = I_C = 1mA, and I_B = 0A. Plug the I_C value into the equation: I_C/C = dv/dt (C = 1uF). We know that the slope of the voltage change is 1000V/second, or 1 Volt per millisecond. Now, we know the capacitor voltage raises at 1V/ms from -10V, but we also need to know where is the upper limit. Looking back to the BJT basics about operating regions and BJT's 2-diode model, it is not hard to identify that this PNP BJT must operate in "Saturation" region (NOT IN "ACTIVE" REGION!). The boundary of that region is V_BC <= 0.7V (I hope everybody is able to solve for this). Hence, 0.7V will be the upper limit for capacitor voltage. At this point, you will have a flat line at Vo = -10V before t = 0. and raises at 1V/ms for 10.7ms and hit Vo = 0.7V. From t = 10.7ms and on, the Vo stays at 0.7V.
One take-home test was to design a circuit to solve a problem which probably originated from a project they were working on. Another one was to design a piece of software in C++. Afterwards, I was given a 3rd test for system design/integration of a sensor system/network for one of their ongoing projects, which caught me a big surprise! I knew it's their actual project since they even sent me pdf file of their internal drawing which was generated about a month ago.
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