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Project Electrical Engineer interview questions shared by candidates

## Top Interview Questions

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### Q2: A pnp transistor with its base connected to a voltage source, the V source is connected to a +10V source. The emitter of the transistor is connected to a resistance, and then to the same +10V source. The collector side is connected to a capacitor, which is not charged at t=0-. Given the graph of Vsource = 10 V stepping up at t = 0 to further, draw the graph of Vout. Vout is between the point of collector and capacitor.

I just made it back from Lutron's HQ and I was asked for the same question. My first approach will be identifying a PNP BJT, and elaborating all 4 BJT operating regions. Before t = 0, since q = 0, by using Q = CV, we can tell that the voltage across the capacitor is 0. Hence, Vo = -10V before t = 0. Recall the capacitor's current equation: I = C*(dv/dt), we can solve for the slope of changing voltage -&gt; dv/dt = I/C. Here, I is simply the BJT's collector current, which can be found by looking at the BJT's emitter current. Given that the (beta) parameter is infinite, we see the base current to be 0. Now, at this point, we need to look for I_E. Since the R is given to be 9.3k, and VEE = 10V, it is natural to assume V_EB = 0.7V, and thus the voltage across R = 9.3V. Therefore, I_E = 9.3/9300 = 1mA. Voila, we now values for all currents: I_E = I_C = 1mA, and I_B = 0A. Plug the I_C value into the equation: I_C/C = dv/dt (C = 1uF). We know that the slope of the voltage change is 1000V/second, or 1 Volt per millisecond. Now, we know the capacitor voltage raises at 1V/ms from -10V, but we also need to know where is the upper limit. Looking back to the BJT basics about operating regions and BJT's 2-diode model, it is not hard to identify that this PNP BJT must operate in "Saturation" region (NOT IN "ACTIVE" REGION!). The boundary of that region is V_BC &lt;= 0.7V (I hope everybody is able to solve for this). Hence, 0.7V will be the upper limit for capacitor voltage. At this point, you will have a flat line at Vo = -10V before t = 0. and raises at 1V/ms for 10.7ms and hit Vo = 0.7V. From t = 10.7ms and on, the Vo stays at 0.7V. Less

ANS: Vout should be constantly -10V until t=0, and will hit V=0 V linearly from V=-10 V after t=0. Less

Hi, Can you explain why it linearly increases? Are you assuming that Collector is tied to -10V? The pnp transistor is completely cutoff for the given biasing. The only way the capacitor is going to charge is through leakage currents. It is very slow and takes a lot of time. Please advise me if my analysis is correct. Less

well, I am an Electrical Engineer as Project Enginner and Interview for the Clients and the per hour rating as the agreement between my employer and client. Less

Currently i am working in qatar as Project Engg in Qatar Metro Rail Project since 2.5 year. I have 8 year experience electrical work. My Current Company is Redco International W L L. Less

### Look at the other questions posted for analog engineer, it'll probably be the same.

pnp transistor ?- input is a 10V step input, output is -10 before time = 0, at time =0 to steady state there is a dv/dt that is related to the current across the cap , i=C*dv/dt , solve for dt and you have the rise time. lastly Vo steaedy state is 0.7 Less

Please can you send JOB DESCRIPTION OF Project Electrical Engineer - Analog POSITION Less

### How you see yourself in the next five years. A lot of technical questions to make sure you know the stuff they wanted you to know.

The president was not satisfied with my answers. SO good luck~!

What is the salary range to be expected or to quote ? Entry Level

### Most questions has to do with the technicality of your up-to-date experience in interdisciplinary areas. After that is your specific area of trade. Other than that will be how you handled other jobs prior to this one so that they can be sure of your loyalty to them and devotion to the tasks on hands.

Objectively. Never be subjective. People from outside of US like to be treated courteously. Speak slowly because everybody is trying to interpret and engage with you simultaneously. No rush. Because you will be with them for the next however many years until the time is up. Treat them with respect since they are your newly found families. Good Luck. Less

### How would you deal with delay delivering a project?

Mitigation Plans,Recovery Plans,Cost Compensations

### If you were the leader of a group, how would that group benefit?

Know your team. Tackle problems quickly with good feedback. Define roles and responsibilities. Break down barriers. Focus on communication. Pay attention. Less

### Q: What inverters do?

Inverters convert the Direct current into alternating current

### Roleplay as an existing product support staff and solve the specified problem.

Played out my role and got to the bottom of the issue.

### First think they revived CV in-front of me. Question asked by Project manager, 1) How you read SLD? 2) How to lay cable using up-stream and down-stream? 3) What are all the testing need to do before turn-ON?

My answer to PM 1) SLD is for us to understand where to take power source and where have to supply for utilities. 2) Cable have to lay as per the current ampere ratings requirements. 3) Before Turn-ON must have to do Cable megger test, Continuity test, Phase rotation test. Less

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