Rtl design engineer Interview Questions


Rtl Design Engineer interview questions shared by candidates

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Rtl Design Engineer was asked...April 7, 2019

Consumtions with and without pipeline, how to test ASICs, how would you get to know if a number is a power of 2.

3 Answers

Bitwise xor should do it.

x is power of 2 if (x & (x-1) == 0) is true

Can you add up the bits serially and check the sum is 1?

Imagination Technologies

There are 5 holes in a line, and there is a rat in one of it. Each turn the rat will move either left or right, but never stay in the same hole, and each turn you can check one hole. The holes are in a line so when the rat reach one end, it must move back in the next turn. What is your strategy to catch that rat?

3 Answers

start with middle move to 2nd and check twice and move to 3rd and then 4th and check 4th twice.. right? OR you start anywhere just move sequentially and check 2nd and 4th place twice Less

middle to 2nd not needed

Keep checking middle one, worst case delay is 4 check, and you should find it by then!! Less


How to detect power of "2" in a given binary number sequence with minimum hardware? For example detect "0001", "0010", "0100", "1000" etc. in incoming series.

2 Answers

Check if [ n & (n-1) == 0 ] or [n & -n == n]

Bitwise xor

Micron Technology

write a verilog code for sequence detector fsm 1001

2 Answers

Hold, setup time. Min clk freq based on tdq delay, tprop delay...

Could you tell more about the other Verilog , timing, coding questions that you were asked in all the rounds? Thanks! Less


Mainly focused on set-up and hold time

1 Answers

Almost I had answered all the questions

Intel Corporation

I dint expect behavioral questions like, why should we hire you, tell me about yourself, what do your friends/prof/former employee say about you.

1 Answers

Be prepared with such type of questions, even though rarely do someone ask such questions. Less

about SPI & I2C protocols and about academic projects

1 Answers


Incise Infotech

1.What are called verilog primitives in verilog?

1 Answers

verilog primitives are AND , NAND , NOR , NOT , OR is also called UDP

5G Testbed IIT-Hyd

Write a verilog code for 1011 sequence detector ?

1 Answers

First I draw the FSM diagram of the sequence detector using both Mealy and Moore state machine, After that I wrote the verilog code for the same. Less


Most of the questions required high problem solving skills: simple circuits (e.g. counter or circuits with adders, multipliers and multiplexers) which I had to design and/or modify in order to improve power consumption/latency/throughput

1 Answers

Well to some questions and bad to others, but very useful since for the next interviews hopefully I will be more able to think out of the box Less

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