Senior ASIC Design Engineer Interview Questions | Glassdoor

Senior ASIC Design Engineer Interview Questions


Senior asic design engineer interview questions shared by candidates

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which is hard to fix -- setup violation or hold violation? And why?

4 Answers

I answered setup, then they asked again how to fix the setup violation.

Should be the hold time violation. Setup time violation can be solved by increasing the time period; however, hold time violation should be solved by inserting delay into the timing path carefully

I think it depends on which stage the problem is detected. If after tape out, it's absolutely hold time because you cannot easily change the logic of chip. But if it is still in RTL coding stage, hold time may be easily fixed by adding some buffers.

FIFO questions; how do you calculate enough FIFO size when the input rate is N, and the output rate is M.

1 Answer

(Unexpected) What the types of caches?

3 Answers

Timing closure. How noise(cross-talk) affect setup/hold? How metal dimension affect timing?

Tell us about your past work experience and how you could apply it to this position

* A lot of computer architecture questions. * Some simple Verilog questions. * Few software related C/C++, compiler, perl scripting questions. * No behavioral/HR question at all.

design async-fifo and sync-fifo in circuit level

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