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Senior ASIC Design Engineer Interview Questions

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“which is hard to fix -- setup violation or hold violation? And why?”

“If I plan to stay for more than 5 years in the company”

“FIFO questions; how do you calculate enough FIFO size when the input rate is N, and the output rate is M.”

“(Unexpected) What the types of caches?”

“Nothing really, some pros/cons of different physical verification tools, how to filter through 100k+ errors, how to solve chip level LVS issues. Should be easy for experience engineers to answer.”

“The interview was straight forward and aveage”

“* A lot of computer architecture questions. * Some simple Verilog questions. * Few software related C/C++, compiler, perl scripting questions. * No behavioral/HR question at all.”

“design async-fifo and sync-fifo in circuit level”

19 of 9 Interview Questions