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Senior Design Engineer Interview Questions


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which is hard to fix -- setup violation or hold violation? And why?

4 Answers

I answered setup, then they asked again how to fix the setup violation.

Should be the hold time violation. Setup time violation can be solved by increasing the time period; however, hold time violation should be solved by inserting delay into the timing path carefully

I think it depends on which stage the problem is detected. If after tape out, it's absolutely hold time because you cannot easily change the logic of chip. But if it is still in RTL coding stage, hold time may be easily fixed by adding some buffers.

In saturation, the channel region pinches off well before the drain. How does current get from the source to drain then? (Since the channel is pinched off, it does not touch the drain)

3 Answers

A key is broken on your laptop keyboard. How do you work around it until you can get a new keyboard?

5 Answers

Reverse a sentence but keep the individual words in the same order

2 Answers

Most difficult was how would you write a script to calculate the latency of a PCIE bus given a data base of several transactions, and their completions. An easier one that was asked that was unexpected, given I am more HW is: Write a function to detect a one-hot encoded state variable. I sort of bombed it at the interview, but looked into the solution in detail after the interview.

2 Answers

FIFO questions; how do you calculate enough FIFO size when the input rate is N, and the output rate is M.

1 Answer

Array of flops in a register file .. how to reduce power

1 Answer

I don't remember being asked any outright questions, we discussed dimension-conformation, Data-Warehousing fundamentals and Cosmos/Scope basics.

1 Answer

Overall ok . Didn't any one question to be very difficult

1 Answer

Given a base 2 integer, give me an algorithm for detecting if it is a palindrome. What is the run time performance of this?

1 Answer
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