Senior Verification Engineer Interview Questions | Glassdoor

Senior Verification Engineer Interview Questions

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Senior verification engineer interview questions shared by candidates

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Describe a circuit that implements the following truth table using only NAND gates. A B OUT 0 0 1 0 1 1 1 0 0 1 1 1

6 Answers

((A NAND B) NAND C)

out = (A NAND (B NAND B))

out = ((A NAND A) NAND (A NAND A)) NAND (B NAND B)

Describe a function to check if an integer is a power of 2.

5 Answers

A question about managing branching methodology when dealing with IP cores.

1 Answer

There are 5 bowls with 100 candies each. In 4 bowls, all of the candies are 10 grams each. In 1 bowl, all the candies are 9 grams each. Using a digital scale, how can you determine which bowl has the 9 gram candies by using only 1 weighing?

2 Answers

SystemVerilog assertion and functional coverage coding.

There was no really difficult question. If I remember clearly, maybe questions on RTL coding style, like always @(posedge clk, reset_active) begin if(reset_active) do somthing else do something end vs: always @(posedge clk, reset_active) begin if(!reset_active) do something else do something end What is the difference in above two impl's.

mostly UVM verification methodologies and insight on how to debug.

In Person: -simple assembly instructions, verify hazards -complex design, methodology for verification -design memory in c, run times -rotate sorted array, binary search algo with shifted array -reverse linked list

1 Answer

Given an async fifo, tell the testplan --> complicated fifo with lot of requirements..(writes are done by 3 masters. there is an arbiter).

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