Senior Verification Engineer Interview Questions | Glassdoor

# Senior Verification Engineer Interview Questions

31

Senior verification engineer interview questions shared by candidates

## Top Interview Questions

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### Senior Hardware Verification Engineer at NVIDIA was asked...

Jan 29, 2010
 Describe a circuit that implements the following truth table using only NAND gates. A B OUT 0 0 1 0 1 1 1 0 0 1 1 16 Answers((A NAND B) NAND C)out = (A NAND (B NAND B))out = ((A NAND A) NAND (A NAND A)) NAND (B NAND B)Show More ResponsesOUT = (A NAND (B NAND 1)) or out = (A NAND (B NAND B)) like what anonymous said.OUT = A' + B OUT = A' + B.1= A' + B.(A+A') = A'+ BA+ BA'= A'(1+B) + BA = A' +BA= (A.(BA)')' [Demorgans] = (A NAND(A NAND B))out = A' & B' + A' & B + A & B; => A' & B' + B => (A' +B) & (B' +B) => A' + B => (A NAND (B NAND B))

### Senior Hardware Verification Engineer at NVIDIA was asked...

Jan 29, 2010
 Describe a function to check if an integer is a power of 2.5 AnswersFor an integer n: If n is less than 1, return false. If the bitwise & of n and n-1 is 0, return true. Otherwise, return false.Write the number in binary and count the number of ones in that.If the number os ones is only 1 then it the number is indeed a power of 2first check if no is 1 then return false else write the number in binary and then check number of ones in that.if only one 1 is there then its a power of 2Show More ResponsesI think the main idea is to use recursion function, for the integer which is larger than 0, if it is 1 return true, else return function(n-1)See if the sum of all bits is 1. If that's the case then the number is a power of 2.

### Senior Design Verification Engineer at Marvell Semiconductor was asked...

Aug 10, 2014
 A question about managing branching methodology when dealing with IP cores.1 AnswerThe group was working on IP cores and needed to provide their cores to a few groups withing Marvell. It made it necessary for them to do branching and merges. It was a learning about what makes sense in this situation.

### Senior Hardware Verification Engineer at NVIDIA was asked...

Jan 29, 2010
 There are 5 bowls with 100 candies each. In 4 bowls, all of the candies are 10 grams each. In 1 bowl, all the candies are 9 grams each. Using a digital scale, how can you determine which bowl has the 9 gram candies by using only 1 weighing?2 AnswersTake 1 candy from bowl 1, 2 candies from bowl 2, 3 candies from bowl 3, and 4 candies from bowl; and weight them on the digital scale. If the total weight is 100 grams, the 9 gram candies are in bowl 5. If the total weight is 99 grams, the 9 gram candies are in bowl 1. If the total weight is 98 grams, the 9 gram candies are in bowl 2. If the total weight is 97 grams, the 9 gram candies are in bowl 3. If the total weight is 96 grams, the 9 gram candies are in bowl 4.if weighing machine can weigh the bowls: Put 2 bowls on each side, if they weigh equal then last bowl has candies with 9 grams. If the bowl weigh different then weigh the 2 bowls with lower weight and find the lowest weight bowl.

### Senior Verification Engineer at Intel Corporation was asked...

Jul 10, 2017
 SystemVerilog assertion and functional coverage coding.Be the first to answer this question

### Senior Design Verification Engineer at NVIDIA was asked...

Apr 24, 2014
 There were no difficult questions.Be the first to answer this question

### Senior Verification Engineer at PLX Technology was asked...

Jan 30, 2013
 There was no really difficult question. If I remember clearly, maybe questions on RTL coding style, like always @(posedge clk, reset_active) begin if(reset_active) do somthing else do something end vs: always @(posedge clk, reset_active) begin if(!reset_active) do something else do something end What is the difference in above two impl's.Be the first to answer this question

### Senior Verification Engineer at Arm was asked...

Aug 5, 2016
 mostly UVM verification methodologies and insight on how to debug.Be the first to answer this question

### Senior Verification Engineer at NVIDIA was asked...

Nov 1, 2016
 In Person: -simple assembly instructions, verify hazards -complex design, methodology for verification -design memory in c, run times -rotate sorted array, binary search algo with shifted array -reverse linked list1 Answeruse hash table with chunks of available memory as keys evaluate different run times

### Senior Verification Engineer at Oracle was asked...

Apr 8, 2014
 Given an async fifo, tell the testplan --> complicated fifo with lot of requirements..(writes are done by 3 masters. there is an arbiter). Be the first to answer this question
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