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SoC Verification Engineer was asked...June 17, 2015

First interviewer did bus connection verification. so he asked about the protocol of ahb and axi. Then he asked how many vip should be used for their verification environment. I didn't understand the question clearly. Because if we want to keep CPU and the code run on real CPU, we don't need to replace these interfaces with VIPs, but if the CPU needs to be replaced, only other slave/master interfaces need to be replaced by VIPs. After he cleared it, what he wanted to do was to replace all the CPU interfaces and other IP interfaces. The second interviewer asked 2 questions: 1) how to check the module was reset by reading/writing registers? The premise for this was there was no spec for register. 2) how to check an interrupt was generated? There was a bit in the register for the interrupt signal. The third interviewer asked the following questions: 1) virtual memory structure 2) spin lock 3) tomasulo 4) fibonacci generator The last technical interviewer asked: 1) shell questions: search a key word in a file and count how many lines contain the key word 2) Perl sort question: user perl to sort a hash with key or with value 3) set environment variable in Perl 4) fibonacci generator 5) there are 2 buckets: 5 litters and 3 litters, how to get 4 litters of water 6) there is a rectangle pie, remove a small rectangle in that large rectangle, after that, use a straight line to cut the pie to get 2 equal areas. There was another question I forgot who asked: use SystemVerilog to generate address with the following constraint: 0x0 (mem1), 0x4(mem2), 0x8(mem3), 0xC(mem1), 0x10(mem2), 0x14(mem3) ...

3 Answers

The first interviewer: I wrote ahb and axi write protocol, but I forgot how hready worked for ahb protocol, so a little error in hready. For replacing VIPs, just count how many interfaces need to be replaced. The second interviewer: 1) reset the module -> read the register of the module (POR value) -> write the register of the module -> read the written register to make sure the register has been written -> reset the module -> read the register of the module to compare with the previous read POR value. 2) check the register to see if the interrupt bit is set or not -> if it is set, fail the test -> else enable the interrupt and generate interrupt to check if interrupt bit will be set The third interviewer: 1) refer to computer architecture 2) I used the code for spin lock which can reduce coherence issue 3) refer to computer architecture 4) there are 3 ways to realize fibonacci generator if you have learned algorithms: divide & conqueror, iterate and the simplest one. divide & conqueror and iterator will use O(N) memory space for stack or storing the data. The simplest way was: int fab(n) { int a = 1; int sum = 0; int a_tmp; for(int i=0; i $hash{$b}} keys %hash 3) $ENV{var} = "xxx" 4) the same as the previous one 5) 5-3 = 2; 5 - (3-2) = 4 6) cut the pie along the center of the big rectangle and the small rectangle, I got hint in this question For the systemverilog question: use constraint addr_con {addr[31:2] % 3 == 1; addr[1:0] == 0} for mem1. I used it before in Hisilicon, but as it's been years, so I forgot it. Less

Another question is about the difference between i = i + 1 and i++. The interviewer told me that i = i + 1 would be translated to add and i++ would be translated to incr in assembly code. I tried for(int i=0; i<10; i++), for(int i=0; i<10; ++i) and for(int i=0; i<10; i=i+1) using ARM gcc compiler on Ubuntu, the de-assembly code was the same. It was add r2, r2, #1. And I didn't find opcode incr in ARM ISA. Less

Answer to question: Generate address with the following constraint: 0x0 (mem1), 0x4(mem2), 0x8(mem3), 0xC(mem1), 0x10(mem2), 0x14(mem3) -mem1 --> ( 0, 12, 24, 36, 48...) => 4*( 0, 3, 6, 9, 12...) => constrain _mem1 { addr [31:2] % 3 == 0 ; addr[1:0] == 2'b0 } -mem2 --> ( 4, 16, 28, 40, 52...) => 4*( 1, 4, 7, 10, 13...) => constrain _mem1 { addr [31:2] % 3 == 1 ; addr[1:0] == 2'b0 } -mem3 --> ( 8, 20, 32, 44, 56...) => 4*( 2, 5, 8, 11, 14...) => constrain _mem1 { addr [31:2] % 3 == 2 ; addr[1:0] == 2'b0 } Less

Intel Corporation
Soc was asked...January 2, 2018

If there is a high frequency clock and you have a lower frequency gazette what will you use

2 Answers

Use Flip Flops

I also tell that but they discard


Trick question: What port is ICMP?

2 Answers

ICMP is not a port, it’s an application

Can you provide with more questions they asked you in the interview? Thanks


Are you happy to work 12 hour shifts?

2 Answers




My current salary and benefits

2 Answers

I gave them some general figures, but it never should have come up

they are asking because they have the lowest rates that you will ever heard off, I used to work there , Sentinel is recommended for beginners whom are trying to get in the system, they do have a high rates of lay offs. I was one of the employees whom got laid off Less

SOC Analyst was asked...September 8, 2015

What is the main difference between hashing and encryption?

2 Answers

Hashing is not reversible and does not use a key, although it may use a salt to mitigate risk from rainbow table attacks. Encryption is reversible and uses a key. Less

I did not fully understand, so I tried my best to explain that I do understand what each are and where each are used. They later told me exactly what they were looking for and I later googled the question. Less

Intel Corporation
Soc was asked...May 12, 2016

why did you use folded cascode OTA instead of telescopic OTA ?

2 Answers

Input voltage swing range is higher

Were you hired in the Month of May after the hiring freeze started?

Milton Security Group
SOC Analyst was asked...September 5, 2019

Did you cheat by using google on my assessment test?

1 Answers

No, I did not. Feel free to check your cameras.


Describe a recent challenge you had to overcome

1 Answers

I described events surrounding lockdown

StarLink Group

network and security concepts

1 Answers


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