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Verification engineer Interview Questions

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You have 2 pieces of rope, each of which burns from one end to the other in 30 minutes (no matter which end is lit). If different pieces touch, the flame will transfer from one to the other. You cannot assume any rope properties that were not stated. Given only 1 match, can you time 45 minutes?

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Take one rope (Rope A), place it down as a circle. Light match and start burning rope A at the tips that are touching. When the rope completely burns out, 15 minutes will have passed (since both ends are burning and being consumed at once). Hold the second rope (Rope B) straight and place one end so that it will immediately catch fire when the two burning points from (Rope A) finally touch and are just about to burn out. Thus 15 minutes on Rope A + 30 minutes on Rope B gives you 45 mins.

How about this: Fold the first rope double so the ends touch. Lay it down and lay the second rope so it touches the fold of the first rope. Light the ends of the first rope. After 15 minutes the second rope should ignite. Once second rope finishes burning it is 45 minutes. Same principle as above, I just don't want to sit there for 15 minutes in order to light the second rope.... :-)

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PHONE : 1. Pass by value/ pass by reference. Write a function to swap 2 variables - ll u use pass by value or reference ? 2. Do the same to swap 2 objects (how does it change) 2. Detect 11010 sequence with moore and mealy state machines. 3. Use of const ? What ll happen if you declare above 2 objects as const. 4. Explain NB assignment and blocking assignment. About event regions. 5. Fibonacci -- iterative solution and recursive solution. 6. Disadvantages of a recursive solution. 7. Output of this code fragment : reg a,b,c,d,w; assign w = a; initial begin a = 2; c=5; b<=c; a=5; end what is output of all registers. 8. Explain RISC pipeline. What is the problems. 9. Explain about uvm driver etc. ONSITE : round 1: Round Robin Arbiter Design round 2 : (1) Given a stack class implementation (LIFO) - there are 3 methods - push(), pop(), isempty(). Write a class using objects of given class to implement a FIFO. (2) Make best performance Implement the dist functionality in c++. Given a set of weights mimic to provide randomization skewed to the specification (Basically, write a function that would do something similar to a 'dist' in system verilog). round 3 : Given a divide by 3 state machine. Implement a divide by 5 statemachine. How many vectors are needed to verify it. So the circuit takes serial bit inputs and asserts if the number is a multiple of 3 or 5. round 4 : Circuits project. Basic pipeline architecture. Design a pipeline for a histogram processor. In every cycle we get an instruction (CLR, ADD INCR). Handle dependencies using bypass. round 5 : Given a producer and consumer. They are clocked with the same clock. Producer produces 80 writes for 100 clocks (no random). Consumer reads 8 times per 10 clocks. Find the FIFO depth. Write RTL and verify.

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Create a 8 input AND gate using 3 4:1 muxes

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Describe a function to check if an integer is a power of 2.

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You have seven stones and a weighing scale. Six of the stones are equal in weight and one is lighter. How will you figure out which one is lighter ? Minimum tries required to do so ?

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How would you verify a 3 bit and 64 bit adder? Would you adopt the same strategy?

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is run phase top down/bottom up

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Describe a circuit that implements the following truth table using only NAND gates. A B OUT 0 0 1 0 1 1 1 0 0 1 1 1

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First interviewer did bus connection verification. so he asked about the protocol of ahb and axi. Then he asked how many vip should be used for their verification environment. I didn't understand the question clearly. Because if we want to keep CPU and the code run on real CPU, we don't need to replace these interfaces with VIPs, but if the CPU needs to be replaced, only other slave/master interfaces need to be replaced by VIPs. After he cleared it, what he wanted to do was to replace all the CPU interfaces and other IP interfaces. The second interviewer asked 2 questions: 1) how to check the module was reset by reading/writing registers? The premise for this was there was no spec for register. 2) how to check an interrupt was generated? There was a bit in the register for the interrupt signal. The third interviewer asked the following questions: 1) virtual memory structure 2) spin lock 3) tomasulo 4) fibonacci generator The last technical interviewer asked: 1) shell questions: search a key word in a file and count how many lines contain the key word 2) Perl sort question: user perl to sort a hash with key or with value 3) set environment variable in Perl 4) fibonacci generator 5) there are 2 buckets: 5 litters and 3 litters, how to get 4 litters of water 6) there is a rectangle pie, remove a small rectangle in that large rectangle, after that, use a straight line to cut the pie to get 2 equal areas. There was another question I forgot who asked: use SystemVerilog to generate address with the following constraint: 0x0 (mem1), 0x4(mem2), 0x8(mem3), 0xC(mem1), 0x10(mem2), 0x14(mem3) ...

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(Unexpected) What the types of caches?

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