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ASIC Layout Design Engineer Jobs in Bengaluru

69 Jobs

  • 3.9
    Synopsys – Bengaluru
    20 days ago 20d
    Mgr I, ASIC/LayoutDesign Requisition Number 15949BR Hiring Location(s) INDIA - Bangalore Job Category Engineering Hire… Electrical engineering Skills/Experience: Strong technical layout manager to help lead a group of mixed-signal layout engineers…
  • 4.3
    NVIDIA – Bengaluru
    21 days ago 21d
    a Senior ASICEngineer - Design. As a member of our ASIC backend/timing team, you'll be working on product designs, focusing… see: BS or MS in Electrical Engineering or Computer Science 2-5 years of relevant ASICdesign experience ideally with a focus…
  • 4.3
    NVIDIA – Bengaluru
    21 days ago 21d
    SENIOR ASICENGINEER - DESIGN SENIOR ASICENGINEER - DESIGN: As a member of our ASIC backend/timing team, you'll be working… REQUIREMENTS: BS or MS in Electrical Engineering or Computer Science 5+ years of relevant ASICdesign experience ideally with a focus…
  • Free Lancer Vikas Sadineni – Bengaluru
    NEW
    __yrs months nbsp; / Skills : Embedded Vlsi Asic Chip Design, analog LayoutDesign, virtuoso xl gxl, Ic12 1, calibre, pll, Band… yrs monthsExperience in Embedded VLSI ASIC Chip Design ______yrs monthsExp in Analog Layout Designing___________yrs monthsExp in…
  • 3.4
    SanDisk – Bengaluru
    5 days ago 5d
    definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system… Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects…
  • 3.3
    Maxim Integrated – Bengaluru
    19 days ago 19d
    Logic cell circuit design, verification and layout Developed models/views for leading-edge EDA design/layout tools and flows… Requisition Number 4529BR External Posting Title ASIC Library Development Engineer Time Type Full time Pay Rate Type Salary…
  • 4.0
    New Era India Consultancy Private Ltd – Bengaluru
    19 days ago 19d
    and pulse latch layoutdesign Follow design guidelines set forth by the Engineering and Layoutdesign leads Layouts Macros must be… relevant exp in layout contributions towards test chips or products Hands-on experience layout of digital ASICs in leading edge…
  • 3.2
    Western Digital – Bengaluru
    10 days ago 10d
    controller ASIC. This position is responsible for providing leadership of IP level layout activities and coordinating layout resources… controller ASIC. This position is responsible for providing leadership of IP level layout activities and coordinating layout resources…
  • 3.3
    Applied Micro – Bengaluru
    HOT
    DescriptionStaff-Senior Staff-Layout Integration LayoutDesign Physical Verification EngineerExperienced senior level mask designer, specializing… DFM issues, EM, IR analysis and layout techniques Hands on experience in Analog Layoutdesign of various blocks SERDES, PLL, ADCs…
  • 3.2
    Western Digital – Bengaluru
    19 days ago 19d
    Senior Engineer would be responsible for full custom layout of high performance mixed signal IP’s for controller ASIC. Responsible… Senior Engineer, ASIC Development Engineering Location: Bangalore, KA, India Req ID: JR-0000036616…
  • 3.2
    Western Digital – Bengaluru
    18 days ago 18d
    definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system… Principal Engineer, ASIC Development Engineering Location: Bangalore, KA, India Req ID: JR-9999031553 Apply…
  • 3.8
    Intel – Bengaluru
    7 days ago 7d
    relevant SoC/IP/ASICdesign, validation including RTL development. Expertise in design and integration of design blocks, IPs to… creation of the spec, design, verification support. Preferred Skills: Experience with ASIC & FPGA based designs. Experience with implementing…
  • 3.8
    Intel – Bengaluru
    7 days ago 7d
    relevant SoC/IP/ASICdesign, validation including RTL development. Expertise in design and integration of design blocks, IPs to… creation of the spec, design, verification support. Preferred Skills: Experience with ASIC & FPGA based designs. Experience with implementing…
  • 3.8
    Intel – Bengaluru
    NEW
    Modem Hardware MHW Design Team.We are looking for experienced Physical DesignEngineers at our Bangalore Design center .In this position… 5G.You will be part of a talented team of engineers that takes designs from RTL to complete physical implementation, in a fast-paced…
  • 3.8
    Intel – Bengaluru
    5 days ago 5d
    optimizationExperience in CPU/ASICdesign methodology and flow development, particularly in the RLS, Structural Design, APR & low power optimization… multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel…
  • 3.8
    Intel – Bengaluru
    5 days ago 5d
    optimizationExperience in CPU/ASICdesign methodology and flow development, particularly in the RLS, Structural Design, APR & low power optimization… multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel…
  • 3.8
    Intel – Bengaluru
    5 days ago 5d
    optimizationExperience in CPU/ASICdesign methodology and flow development, particularly in the RLS, Structural Design, APR & low power optimization… multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel…
  • 3.8
    Intel – Bengaluru
    5 days ago 5d
    optimizationExperience in CPU/ASICdesign methodology and flow development, particularly in the RLS, Structural Design, APR & low power optimization… multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel…
  • 4.0
    New Era India Consultancy Private Ltd – Bengaluru
    19 days ago 19d
    and pulse latch layoutdesign Follow design guidelines set forth by the Engineering and Layoutdesign leads Layouts Macros must be… relevant exp in layout contributions towards test chips or products Hands-on experience layout of digital ASICs in leading edge…
  • 3.2
    Western Digital – Bengaluru
    10 days ago 10d
    /IO Senior DesignEngineer would be responsible for designing high performance mixed signal IP’s for controller ASIC. Responsible… Electronics/Electrical Engineering with 4+ years of experience in High Speed IOs & Analog IPs design/architecture and layout. Experience…
  • 3.8
    Intel – Bengaluru
    NEW
    in high performance ASIC/SOC physical design. Strong expertise in the RTL2GDSII flow development or design implementation in leading… Qualifications: BS or MS with 6-15 years of experience in ASIC/SOC Physical Design RTL2GDS. Ability to multi-task and flexibility to work…
  • 2.8
    GLOBALFOUNDRIES – Bengaluru
    13 days ago 13d
    extensive experience with the layout of analog and some high speed custom digital circuits in ASIC applications. Applicants must… SerDes LayoutEngineer: GLOBALFOUNDRIES is looking for a strong technical leader to join our world-class Layout team! Circuit…
  • 3.8
    Intel – Bengaluru
    18 days ago 18d
    Hardware MHW Design Team.We are looking for an experienced Physical DesignEngineer Lead at our Bangalore Design center .In this… the design and development of Intel's multimode cellular modem baseband 2G/3G/LTE/5G.As a Senior Physical DesignEngineer you…
  • 3.8
    Intel – Bengaluru
    13 days ago 13d
    relevant SoC/IP/ASIC physical design and verification. Understand system and package implications of the silicon design decisions.… multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of SoC physical design flow from high-level…
  • 3.4
    Achronix Semiconductor – Bengaluru
    6 days ago 6d
    employee is responsible for complete physical design of large and complex ASIC and FPGA blocks. The employee is expected to take… Achronix products. Position Profile Name: Senior DesignEngineer, Physical Design Requisition No.: 6400-1027 Type of Position…
  • 3.4
    Achronix Semiconductor – Bengaluru
    6 days ago 6d
    complete physical design of multiple large and complex ASIC and FPGA blocks, and may also contribute to full chip design and integration… Achronix products. Position Profile Name: Staff Engineer, Physical Design Requisition No.: 6400-1024 Type of Position:…
  • 3.8
    Intel – Bengaluru
    13 days ago 13d
    integration, logic design skills and ASIC flow. Additional qualifications include: Strong SOC/CPU micro arch/design background.Strong… multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel…
  • 3.8
    Microchip Technology – Bengaluru
    NEW
    product and test engineering, marketing, development systems, technology development, CAD, layout and other design organizations… optimization, static timing analysis, and design verification using an industry leading ASICdesign flow. It will require a proactive…
  • 3.8
    Intel – Bengaluru
    13 days ago 13d
    relevant SoC/IP/ASIC physical design and verification. Understand system and package implications of the silicon design decisions.… multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of SoC physical design flow from high-level…
  • 3.4
    Achronix Semiconductor – Bengaluru
    6 days ago 6d
    complete physical design of multiple large and complex ASIC and FPGA blocks, and will also contribute to full chip design and integration… verification Expertise with physical design and verification tools A strong understanding of layout DRC rules and concepts, and device…
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