ASIC Physical Design Engineer Jobs in Fremont, CA | Glassdoor

ASIC Physical Design Engineer Jobs in Fremont, CA

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  • Approgence – San Jose, CA
    Est. Salary $77k-$109k
    5 days ago 5d
    Job Title : ASIC Physical Design Engineer Job Location : San Diego & San Jose, CA Job Description : This person will… complete physical design. He will identify physical design issues in early stage, working with RTL engineer to fix. He will isolate…
  • 3.9
    Inphi Corporation – Santa Clara, CA
    Est. Salary $221k-$288k
    26 days ago 26d
    Physical Design Engineer Principal Engineer to lead Physical Design activities on the next high complexity ASIC/advanced technology… technology node. Candidate should be familiar with all phases of ASIC design from synthesized gates to GDS. This includes floorplanning…
  • 4.3
    NVIDIA – Santa Clara, CA
    Est. Salary $110k-$155k
    25 days ago 25d
    Accountable for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation… We are now looking for a Senior Physical Design Engineer Nvidia has continuously reinvented itself over two decades. Our invention…
  • 3.0
    Fujitsu – Sunnyvale, CA
    Est. Salary $100k-$138k
    14 days ago 14d
    Design for ASIC using Socionext Advanced Standard Cell technology. The Staff Physical Design Engineer will have opportunities to work… MSEE preferred. Experience in ASIC/COT design flow. Experience in Physical Design Implementation which includes Floorplan…
  • Fujitsu Network Communications – Sunnyvale, CA
    14 days ago 14d
    Design for ASIC using Socionext Advanced Standard Cell technology. The Staff Physical Design Engineer will have opportunities to work… MSEE preferred. Experience in ASIC/COT design flow. Experience in Physical Design Implementation which includes Floorplan…
  • 3.9
    Inphi Corporation – Santa Clara, CA
    26 days ago 26d
    TIAs, and 10G/40G/100G Physical Layer ICs. Recently, Inphi announced the industry first 100G PAM4 ASIC and linear TIA that double… Staff Engineer, Analog Design Engineering | Santa Clara, Ca, United States Inphi Background Inphi Corporation, a high-speed…
  • 4.3
    NVIDIA – Santa Clara, CA
    Est. Salary $98k-$139k
    11 days ago 11d
    ll be doing: Drive physical design and timing convergence of high-frequency low-power CPU, GPU, and/or ASIC at block level, cluster… and hands-on skills in RTL/Logic design for timing closure desired. Knowledge in physical design and optimization e.g. placement…
  • 3.7
    Palo Alto Networks – Santa Clara, CA
    Est. Salary $105k-$142k
    11 days ago 11d
    FPGA and ASIC design engineer to join the FPGA and ASIC design team. This individual will be a key member of the ASIC design team… every aspect of ASIC/FPGA design, working closely with the product marketing, system, software, and ASIC/FPGA design and verification…
  • 2.9
    Fortive – Santa Clara, CA
    Est. Salary $97k-$127k
    1 days ago 17hr
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • 3.5
    Broadcom – Santa Clara, CA
    Est. Salary $119k-$156k
    Today 10hr
    years with MSEE/MSCE in ASIC Physical Design from RTL to GDSII Strong experience in Physical Design – place and route; Floorplanning… for the physical design of all chips in these lines of business. Your primary job responsibility is to perform physical design…
  • 4.3
    NVIDIA – Santa Clara, CA
    13 days ago 13d
    need to see: BS in Electrical or Computer Engineering, MS preferred ASIC design (Verilog coding) and verification RTL static… Formal Equivalence Checking, STA and Physical Design knowledge or experience Prefer hands-on design or implementation experience on…
  • 3.7
    Xilinx – San Jose, CA
    Today 2hr
    convolutional networks (DCNN) and the software or hardware (ASIC) realization of these algorithms is highly valuable for this… at least one of the following technologies: software, FPGA or ASIC. Skills – the candidate would have skills in several, but…
  • Approgence – Santa Clara, CA
    12 days ago 12d
    for a senior expert in SoC Physical Design and RTL Delivery Management for advanced modem Baseband ASIC. - Provide technical support… Job Title : SoC Physical Design and RTL Delivery Lead / Principal Engineer Job Location : Santa Clara, CA Job Description…
  • 3.2
    Sony Electronics – San Jose, CA
    Est. Salary $90k-$123k
    10 days ago 10d
    specification through design, implementation, and device validation. Skills required: Knowledge in ASIC/SOC design methodology.… microarchitecture documentation. Synthesizable RTL coding experience. Physical design experience including synthesis and timing closure. Hardware…
  • 4.3
    NVIDIA – Santa Clara, CA
    Est. Salary $112k-$143k
    7 days ago 7d
    are now looking for an ASIC Engineer - Clocks The NVIDIA Clocks group is looking for a top ASIC engineer with extensive experience… Collaborate with ASIC front end teams to determine the functional requirements for their unit clocks. Team up with the SOC design team to…
  • 3.9
    Apple – Santa Clara, CA
    Est. Salary $101k-$138k
    12 days ago 12d
    quality design. Key Qualifications This position requires thorough knowledge of the ASIC design flow, FE and Design verification… least 10+ years experience in ASIC design flow •Proven track record of high performance designs in high volume production for…
  • 3.7
    Xilinx – San Jose, CA
    Today 2hr
    convolutional networks (DCNN) and the software or hardware (ASIC) realization of these algorithms is highly valuable for this… at least one of the following technologies: software, FPGA or ASIC. Skills – the candidate would have skills in several, but…
  • 3.1
    International Rectifier – Milpitas, CA
    7 days ago 7d
    Infrastructure Sensing and includes Design and Development of Control ICs, Customized chips (ASICs), Discrete low-voltage and high-… amplifier, Low-voltage and high voltage driver ICs, MEMS and ASICs for silicon microphones, RF antenna switches, RF power transistors…
  • 2.8
    Global Foundries – Santa Clara, CA
    Est. Salary $81k-$110k
    4 days ago 4d
    Summary of Role: The Front End Processing (FEP) ASIC Design Center engineer works with clients and the world-class GLOBALFOUNDIRES… innovation with teams of physical design, timing, test and other FEP engineers to get our clients' leading-edge designs to market. Essential…
  • 3.4
    AMD – Sunnyvale, CA
    Est. Salary $108k-$137k
    3 days ago 3d
    CPU, SOC or ASIC environment Demonstrates expertise in the following: Processor Architecture Logic Design RTL Coding… Preferred Education and Skills: Background in other aspects of ASIC implementation, especially with Synthesis flow and Static Timing…
  • 3.7
    Xilinx – San Jose, CA
    Est. Salary $124k-$167k
    Today 5hr
    convolutional networks (DCNN) and the software or hardware (ASIC) realization of these algorithms is highly valuable for this… at least one of the following technologies: software, FPGA or ASIC. Skills – the candidate would have skills in several, but…
  • 3.1
    International Rectifier – Milpitas, CA
    Est. Salary $79k-$135k
    4 days ago 4d
    Infrastructure Sensing and includes Design and Development of Control ICs, Customized chips (ASICs), Discrete low-voltage and high-… has a strong engineering background in power electronics acquired by working as Designer or Application Engineer Experience in…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $121k-$170k
    6 days ago 6d
    methodologies that enable a highly efficient design environment for all ASIC engineers. Behind everything our users see online… complex ASIC designs. This is a highly cross-functional and central role that will require interactions with numerous ASIC development…
  • 3.4
    Advanced Micro Devices – Sunnyvale, CA
    Est. Salary $86k-$128k
    6 days ago 6d
    CA: ASIC/ Layout Design Engineer 2 CA0117: Support tools& flows used for pre-silicon verification; Perform debug; Design& implement… implement ASIC functional blocks. Design Engineer 2 CA0217: Contribute to functional verification of blocks of complete ASICs& IP cores…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $110k-$147k
    5 days ago 5d
    As a Physical Design Engineer, you will leverage your strong technical background to execute the back-end design of ASICs that… Experience designing high-performance ASICs in advanced process nodes and with front-end design tools. Experience interacting and driving…
  • 3.7
    Synopsys – Mountain View, CA
    5 days ago 5d
    Verilog/VHDL) and a strong understanding of ASIC design flows, VLSI, and/or CAD engineering. Knowledge of competitive EDA tool products… and maintains lines of communication with design engineering on issues such as design considerations for product reliability.…
  • 3.7
    Synopsys – Mountain View, CA
    3 days ago 3d
    Business Title ASIC Physical Design Engr, Sr II Requisition Number 12911BR Hiring Location(s) USA - California - Mountain… has solid engineering understanding of the underlying concepts of IC design - has intimate knowledge of the full design cycle from…
  • 3.9
    Apple – Santa Clara, CA
    Est. Salary $105k-$147k
    4 days ago 4d
    specifications and converting them to design Experience designing high performance, low power ASICs/SOCs from scratch Experience in… years work experience in the area of RTL Logic Design of multi-million gate ASICs Hands on experience for all aspects of the chip…
  • 3.0
    Rambus – Sunnyvale, CA
    7 days ago 7d
    collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation… packaging challenges in high-speed interfaces/Physical layers Track record of design and production of serial interface PHYs Track…
  • 3.6
    Intel – Santa Clara, CA
    Est. Salary $105k-$142k
    4 days ago 4d
    tools; UVM/OVM verification methods -Synopsys ASIC design tools - VCS simulator, Design Compiler, IC Compiler -Formal verification… corresponding design modifications and optimizations as required to achieve power and performance targets. -Execution of ASIC logic synthesis…
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