Job Type
Date Posted
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Distance

Senior ASIC Physical Design Engineer Jobs in Fremont, CA

57 Jobs

  • 4.0
    Apple – Santa Clara, CA
    $127k-$171k(Glassdoor est.)
    19 days ago 19d
    SeniorASICDesignEngineer - Fabric Job Number: 52464960 Santa Clara Valley, California, United States Posted: Nov. 28… position requires thorough knowledge of the ASICdesign flow, front end RTL coding and Design verification, synthesis, scripting and…
  • 4.3
    NVIDIA – Santa Clara, CA
    $134k-$177k(Glassdoor est.)
    21 days ago 21d
    looking for a SeniorASIC Floorplan DesignEngineer: NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement… routing congestion issues with physical and ASICdesign teams by influencing early design and physical implementation decisions.…
  • Approgence – San Jose, CA
    $88k-$118k(Glassdoor est.)
    19 days ago 19d
    perform bit-exact simulation. Modem ASICDesign team is working with physicaldesignengineer to deliver netlist, spec timing constraints… Job Title : SeniorASIC/ RTL DesignEngineer Job Location : San Diego & San Jose, CA Job Description : This is a…
  • 4.1
    Quantum Tech USA – San Jose, CA
    $99k-$131k(Glassdoor est.)
    24 days ago 24d
    Job Title: Senior / Lead ASICDesignEngineers Location: San Jose, CA Duration : 6-8 months contract Roles & Responsibilities… MATLAB, modeling) Physical Layer Design (USB, HDMI, DDR, MIPI) Digital Design for Mixed Signal ASICs (PLL, Phase-Lock-Loop…
  • 2.9
    Seagate Technology – Fremont, CA
    14 days ago 14d
    implementation, timing analysis and ASICphysicaldesign methodology for large scale VLSI design. Experience/Education: Seeking… 171279 Senior Staff Physical Layout Designer (Open) Seagate delivers advanced digital storage solutions to meet the needs…
  • 3.5
    Cavium, Inc. – San Jose, CA
    $87k-$113k(Glassdoor est.)
    NEW
    processors. You will work directly with senior members of the ASIC team to learn and design state of art high speed digital systems. Responsibilities… As a new graduate engineer, you would contribute as a designengineer developing the next-generation of multi-core processors.…
  • 2.7
    SK Hynix Memory Solutions – San Jose, CA
    $102k-$141k(Glassdoor est.)
    21 days ago 21d
    Work with PhysicalDesign team to implement design Qualifications: BS, MS or PhD degree in Electrical Engineering or Computer… perform timing analysis Work with Design Verification and emulation team to validate design Develop functional models for architectural…
  • 3.9
    Xilinx – San Jose, CA
    $124k-$181k(Glassdoor est.)
    7 days ago 7d
    software engineer to be part of the Xilinx Vivado Physical Implementation team. This team is responsible for design, implementation… Familiar with state of the art placement/routing/physical synthesis algorithms for ASICs and/or FPGAs. Expert with C , data structures…
  • 4.0
    Apple – Santa Clara, CA
    $116k-$161k(Glassdoor est.)
    12 days ago 12d
    experience in USB related SOC/IP design. 8+ years of RTL Logic Design experience of multi-million gate ASICs Familiarity with USB standards… Senior USB Design Integration Engineer Job Number: 113290233 Santa Clara Valley, California, United States Posted: Nov.…
  • 4.0
    Apple – Santa Clara, CA
    $116k-$161k(Glassdoor est.)
    14 days ago 14d
    Senior PCIe Design Integration Engineer Job Number: 113287753 Santa Clara Valley, California, United States Posted: Nov… work experience: 8+ years of RTL Logic Design experience of multi-million gate ASICs Hands on experience for all aspects of…
  • 4.0
    Cisco Systems – San Jose, CA
    19 days ago 19d
    state-of-the-art design, verification and physicaldesign methodologies created by one of the most advanced ASIC teams in the world… phase of the ASIC development process from architecture definition, implementation, verification, physicaldesign, lab bring-up…
  • 3.7
    Microchip Technology – San Jose, CA
    $71k-$96k(Glassdoor est.)
    NEW
    Systems DesignEngineer to join the advance technology and products group. As a senior member of the team, the designer will be… complex, highly integrated ASICsDesign documentation and IP generation LI-JL1 Job Requirements Qualifications…
  • 3.4
    Dialog Semiconductor – Campbell, CA
    $101k-$136k(Glassdoor est.)
    11 days ago 11d
    continued growth, we seek a Senior Digital DesignEngineer. The role Working in the Digital Design - Power Conversion Business… 8+ years of direct experience in ASIC/IC design with deep knowledge of whole IC design flow from RTL coding and verification…
  • 3.9
    Infineon Technologies – Milpitas, CA
    9 days ago 9d
    Infrastructure Sensing and includes Design and Development of Control ICs, Customized chips (ASICs), Discrete low-voltage and high-… Senior Staff Engineer, Applications At a glance Do you offer strong business acumen and customer orientation? Do you…
  • 4.0
    Apple – Santa Clara, CA
    $140k-$211k(Glassdoor est.)
    24 days ago 24d
    10+ years of work experience. RTL Logic Design experience of multi-million gate ASICs Hands on experience for all aspects of… Description As a SeniorDesign Manager, you will have responsibilities spanning all aspects of SoC design and chip bring up:…
  • Approgence – San Jose, CA
    $88k-$118k(Glassdoor est.)
    13 days ago 13d
    perform bit-exact simulation. Modem ASICDesign team is working with physicaldesignengineer to deliver netlist, spec timing constraints… silicon verification support. Modem ASICDesign team is working with system engineer to understand wireless standards and define…
  • 3.9
    Synopsys – Mountain View, CA
    $113k-$154k(Glassdoor est.)
    8 days ago 8d
    , MSEE preferred, and 5+ years of SOC design experience. This should include ASICdesign with experience using place and route… meet the customer’s needs, a strong working knowledge of ASICdesign and the Synopsys IP product information is required. A good…
  • 3.1
    Fujitsu – Sunnyvale, CA
    $123k-$185k(Glassdoor est.)
    5 days ago 5d
    Science or Electrical Engineering. 8 to 10 years of hands On RTL Coding, Synthesis & Launching multiple ASIC Products. Demonstrated… familiar with ARM architecture Be familiar with ASIC frontend flow, logic design, RTL coding, verification Be familiar with Hardware…
  • 4.3
    NVIDIA – Santa Clara, CA
    $107k-$149k(Glassdoor est.)
    8 days ago 8d
    be doing: Drive physicaldesign and timing convergence of high-frequency low-power CPU, GPU, and/or ASIC at block level, cluster… and hands-on skills in RTL/Logic design for timing closure desired. Knowledge in physicaldesign and optimization e.g. placement…
  • Approgence – Santa Clara, CA
    20 days ago 20d
    looking for a senior expert in SoC PhysicalDesign and RTL Delivery Management for advanced modem Baseband ASIC. Provide technical… Job Title : SoC PhysicalDesign and RTL Delivery Lead / Principal Engineer Job Location : Santa Clara, CA Job Description…
  • 3.8
    Intel – San Jose, CA
    13 days ago 13d
    algorithms. We are looking for engineers with expertise who have developed similar technologies for ASIC/FPGA tools. Responsibilities… timing analysis, interconnect modelling and other logical/physicaldesign concepts. We are currently recruiting for multiple openings…
  • 4.0
    Apple – Santa Clara, CA
    $106k-$144k(Glassdoor est.)
    25 days ago 25d
    IP/SoC design: Previous experience in multimedia IP design and integration. Industry exposure to and knowledge of ASIC/FPGA design… Description As a senior IP Designengineer you will have responsibilities spanning all aspects of multimedia IP design: Will be responsible…
  • 4.4
    Google – Mountain View, CA
    $112k-$152k(Glassdoor est.)
    7 days ago 7d
    As a PhysicalDesignEngineer on the chip implementation team, you will work on the physical implementation of ASICs using advanced… equivalent practical experience. 4 years of experience in ASICphysicaldesign flows and methodologies in 7nm, 16nm and 28nm process…
  • 4.7
    Macropace Technologies – San Jose, CA
    EASY APPLY
    $82k-$114k(Glassdoor est.)
    6 days ago 6d
    PHYSICALDESIGNENGINEER San Jose, CA Fulltime/ Contract Job Description: You will be part of a PhysicalDesign team… and Physical Verification closure of SoC/sub-chips. Desired Skills and Experience: Experience in PhysicalDesign Handled…
  • 3.8
    Intel – San Jose, CA
    7 days ago 7d
    algorithms. We are looking for engineers with P&R expertise who have developed similar technologies for ASIC/FPGA. Responsibilities for… other physicaldesign concepts. Qualifications BS/MS or PhD preferred in Computer Science, Computer Engineering, or related…
  • 3.8
    Intel – San Jose, CA
    5 days ago 5d
    algorithms. We are looking for engineers with expertise who have developed similar technologies for ASIC/FPGA tools. Responsibilities… logical/physicaldesign concepts. Qualifications Minimum Qualifications: BS in Electrical Engineering, Computer…
  • 4.0
    Apple – Santa Clara, CA
    $127k-$193k(Glassdoor est.)
    24 days ago 24d
    + years of work experience.   RTL Logic Design experience of multi-million gate ASICs   Hands on experience for all aspects of… Description As a SeniorDesign Manager, you will have responsibilities spanning all aspects of SoC  design and chip bring up…
  • 3.6
    Broadcom – San Jose, CA
    $92k-$125k(Glassdoor est.)
    22 days ago 22d
    implementations This requisition is approved for the Senior Staff Engineer level. At this level, candidates should have BSEE w/… implementing, and testing high performance communications/networking ASIC products. Candidates with other qualifications will be considered…
  • 3.9
    Synopsys – Mountain View, CA
    $96k-$132k(Glassdoor est.)
    11 days ago 11d
    VHDL) and has a strong understanding of ASICdesign flow, VLSI, and/or CAD engineering. Knowledge of competitive EDA tool products… Synthesis, Simulation, Verification, Place and Route, Design Reuse and/or PhysicalDesign is preferred. Typically requires a minimum…
  • 3.8
    Intel – San Jose, CA
    5 days ago 5d
    algorithms. We are looking for engineers with expertise who have developed similar technologies for ASIC/FPGA tools. Responsibilities… timing analysis, interconnect modelling and other logical/physicaldesign concepts. We are currently recruiting for multiple openings…
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