Senior ASIC Physical Design Engineer Jobs in Fremont, CA | Glassdoor

Senior ASIC Physical Design Engineer Jobs in Fremont, CA

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  • 3.6
    Intel Corporation – Santa Clara, CA
    Today 9hr
    group. We are looking for a senior expert in SoC architecture and design for advanced modem Baseband ASIC. Provide technical leadership… -10+ years' experience with RTL Logic Design of multi-million gate ASICs/ modem ASIC or wireless AP SoC implementation in complex…
  • 3.8
    Infineon Technologies – Milpitas, CA
    Est. Salary $105k-$149k
    7 days ago 7d
    Infrastructure Sensing and includes Design and Development of Control ICs, Customized chips (ASICs), Discrete low-voltage and high-… Senior Field Application Engineer At a glance As part of the North American Regional Sales Team, you will work with…
  • 3.4
    Advanced Micro Devices – Sunnyvale, CA
    Est. Salary $86k-$128k
    7 days ago 7d
    modeling, analysis,& microarchitecture development. Senior ASIC/Layout Design Engineer CA0517: Responsible for functional verification… CA: ASIC/ Layout Design Engineer 2 CA0117: Support tools& flows used for pre-silicon verification; Perform debug; Design& implement…
  • 3.1
    Fortive – Santa Clara, CA
    Est. Salary $97k-$127k
    2 days ago 2d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • 3.7
    Synopsys – Mountain View, CA
    7 days ago 7d
    Verilog/VHDL) and a strong understanding of ASIC design flows, VLSI, and/or CAD engineering. Knowledge of competitive EDA tool products… and maintains lines of communication with design engineering on issues such as design considerations for product reliability.…
  • 3.9
    Apple – Santa Clara, CA
    Est. Salary $122k-$166k
    5 days ago 5d
    Senior ASIC Design Engineer - Cache Job Number: 52167565 Santa Clara Valley, California, United States Posted: Apr. 14,… Qualifications The ideal candidate will have 5+ years of ASIC design experience: 5+ years of development of memory system.…
  • 3.5
    Broadcom – Santa Clara, CA
    Est. Salary $119k-$156k
    2 days ago 2d
    years with MSEE/MSCE in ASIC Physical Design from RTL to GDSII Strong experience in Physical Design – place and route; Floorplanning… Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player Ability to effectively…
  • 3.0
    Fluke Corporation – Santa Clara, CA
    Est. Salary $96k-$125k
    4 days ago 4d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • Approgence – San Jose, CA
    Est. Salary $83k-$110k
    6 days ago 6d
    perform bit-exact simulation. - Modem ASIC Design team is working with physical design engineer to deliver netlist, spec timing constraints… Job Title : Senior ASIC/ RTL Design Engineer with DSP Job Location : San Diego & San Jose, CA Job Description : This…
  • 3.0
    Tektronix – Santa Clara, CA
    Est. Salary $112k-$145k
    4 days ago 4d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • Approgence – San Jose, CA
    Est. Salary $83k-$110k
    6 days ago 6d
    perform bit-exact simulation. - Modem ASIC Design team is working with physical design engineer to deliver netlist, spec timing constraints… silicon verification support. - Modem ASIC Design team is working with system engineer to understand wireless standards and define…
  • 3.2
    Magma Design – Mountain View, CA
    13 days ago 13d
    Verilog/VHDL) and a strong understanding of ASIC design flows, VLSI, and/or CAD engineering. Knowledge of competitive EDA tool products… and maintains lines of communication with design engineering on issues such as design considerations for product reliability.…
  • 3.6
    Intel Corporation – Santa Clara, CA
    Est. Salary $105k-$142k
    12 days ago 12d
    tools; UVM/OVM verification methods -Synopsys ASIC design tools - VCS simulator, Design Compiler, IC Compiler -Formal verification… Job Type: Experienced Hire Senior Graphics Hardware Design Engineer Job Description If you're interested in computer…
  • 3.0
    Rambus – Sunnyvale, CA
    8 days ago 8d
    collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation… Interact with technical leaders of the company and senior staff in engineering, marketing, and corporate development to help ensure…
  • 3.1
    International Rectifier – Milpitas, CA
    Est. Salary $91k-$130k
    19 days ago 19d
    Infrastructure Sensing and includes Design and Development of Control ICs, Customized chips (ASICs), Discrete low-voltage and high-… Senior Field Application Engineer At a glance Do you enjoy the challenge of working in a leading-edge technology environment…
  • 3.2
    Magma Design – Mountain View, CA
    13 days ago 13d
    VHDL) and has a strong understanding of ASIC design flow, VLSI, and/or CAD engineering. Knowledge of competitive EDA tool products… Synthesis, Simulation, Verification, Place and Route, Design Reuse and/or Physical Design is preferred. Typically requires a minimum of…
  • Approgence – Santa Clara, CA
    13 days ago 13d
    looking for a senior expert in SoC Physical Design and RTL Delivery Management for advanced modem Baseband ASIC. - Provide technical… Job Title : SoC Physical Design and RTL Delivery Lead / Principal Engineer Job Location : Santa Clara, CA Job Description…
  • 3.4
    Advanced Micro Devices, Inc. – Sunnyvale, CA
    Est. Salary $87k-$119k
    28 days ago 28d
    introduction and ramp Develop design guidelines and process recipes Collaborate with ASIC design team to define boundaries of… introduction and ramp Develop design guidelines and process recipes Collaborate with ASIC design team to define boundaries of…
  • 3.3
    Altera – San Jose, CA
    Est. Salary $96k-$131k
    12 days ago 12d
    experience in logic/physical synthesis algorithm design and optimization Knowledge of C/C++ and strong software engineering skills are… and/or industry background in synthesis algorithms (either in ASIC and/or FPGA domains). The successful candidate's minimum qualifications…
  • 3.7
    Synopsys – Mountain View, CA
    28 days ago 28d
    VHDL) and has a strong understanding of ASIC design flow, VLSI, and/or CAD engineering. Knowledge of competitive EDA tool products… Synthesis, Simulation, Verification, Place and Route, Design Reuse and/or Physical Design is preferred. Typically requires a minimum of…
  • 3.2
    Magma Design – Mountain View, CA
    Est. Salary $74k-$108k
    13 days ago 13d
    VHDL) and has a strong understanding of ASIC design flow, VLSI, and/or CAD engineering. Knowledge of competitive EDA tool products… Synthesis, Simulation, Verification, Place and Route, Design Reuse and/or Physical Design is preferred. Typically requires a minimum of…
  • Approgence – Santa Clara, CA
    Est. Salary $99k-$138k
    14 days ago 14d
    Job Title : Senior DSP/RF SW Development Engineer Job Location : Santa Clara, CA Job Description : This is a Full Time… Electrical Engineering or equivalent - Background in communication systems and signal processing - Strong experience in Physical (PHY…
  • 3.0
    Rambus – Sunnyvale, CA
    Est. Salary $164k-$213k
    28 days ago 28d
    collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation… Interact with technical leaders of the company and senior staff in engineering, marketing, and corporate development to help ensure…
  • 3.7
    Synopsys – Mountain View, CA
    Est. Salary $107k-$146k
    20 days ago 20d
    VHDL) and has a strong understanding of ASIC design flow, VLSI, and/or CAD engineering. Knowledge of competitive EDA tool products… Synthesis, Simulation, Verification, Place and Route, Design Reuse and/or Physical Design is preferred. Typically requires a minimum of…
  • 4.3
    NVIDIA – Santa Clara, CA
    Est. Salary $110k-$154k
    27 days ago 27d
    We are now looking for a Senior Physical Design Engineer Nvidia has continuously reinvented itself over two decades. Our invention… Accountable for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation…
  • Approgence – Santa Clara, CA
    Est. Salary $91k-$125k
    27 days ago 27d
    in SoC Physical Design and RTL Delivery Management for advanced modem Baseband ASIC. - Provide technical support for a team of… Title : SoC Physical Design Lead Job Location : Santa Clara, CA Job Description : - We are looking for a senior expert in…
  • 4.7
    Battery Ventures – Santa Clara, CA
    22 days ago 22d
    silicon, chip, SOC, ASIC, full-chip STA, Primetime, full-chip timing, STA, static timing analysis, ASIC timing… Senior Full-Chip Static Timing Analysis Engineer As a member of Fungible's team, you will be responsible for all aspects of…
  • 3.5
    Broadcom – San Jose, CA
    Est. Salary $86k-$119k
    15 days ago 15d
    implementations This requisition is approved for the Senior Staff Engineer level. At this level, candidates should have BSEE w/… implementing, and testing high performance communications/networking ASIC products. Candidates with other qualifications will be considered…
  • 3.3
    Micron – Milpitas, CA
    Est. Salary $105k-$139k
    30+ days ago 30d+
    of these products. You will collaborate with ASIC designers and other engineering departments including system architecture, hardware… Req Id: 75602  As a Senior Module Design Engineer at Micron Technology, Inc., within the Compute and Networking Business Unit…
  • 2.9
    Avago Technologies – San Jose, CA
    Est. Salary $91k-$126k
    17 days ago 17d
    implementations This requisition is approved for the Senior Staff Engineer level. At this level, candidates should have BSEE w/… implementing, and testing high performance communications/networking ASIC products. Candidates with other qualifications will be considered…
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