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Mask Design Engineer Jobs

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  • 4.0
    Linear Technology – Santa Barbara, CA
    16 days ago 16d
    Analog Devices, is seeking a highly skilled MaskDesigner / Physical Layout Engineer for our Santa Barbara, CA location. We develop… position. • Associates or bachelor’s degree in Electrical Engineering • Three years of relevant IC layout experience • Strong background…
  • 3.7
    Intel – Folsom, CA
    8 days ago 8d
    Qualifications: 2 year technical degree in VLSI or Physical Design/MaskDesign Ability to work well in a team environment Experience… tools Ability to work with engineers on scheduling, execution, and verifying complex designs Qualifications Responsibilities…
  • 3.4
    Gonzer Associates, L.J. – Mount Kisco, NY
    Est. Salary $54k-$74k
    9 days ago 9d
    opening for a Photolithography MaskDesignEngineering position in Mount Kisco, NY. This engineer will interact with and contribute… Bachelor's or Master's Degree in Engineering or Scientific field Experience with Photolithography MaskDesign Have a working knowledge…
  • 3.1
    WAVSYS – San Diego, CA
    9 days ago 9d
    Job Description QCT RF/Analog design group is seeking experienced Mask Layout Designers to fulfill both block and project lead… on experience and expertise. The layout designer will be responsible for physical design of RF and analog circuits in a fast paced…
  • 3.1
    Cypress Semiconductor – San Jose, CA
    Est. Salary $79k-$111k
    NEW
    Job Description Cypress’ RFIC design group is seeking experienced mask layout designers to fulfill both large block level… Secondary Market: Palo Alto Job Segment: DesignEngineer, Engineer, Engineering
  • 3.1
    Cypress Semiconductor – Lynnwood, WA
    12 days ago 12d
    Sr Analog MaskDesignEngineer Requisition Id:- 5142 Job Description Cypress Semiconductor is recruiting… Bellevue Job Segment: Electrical Engineering, DesignEngineer, Automotive, Engineering
  • Novus Resources – San Jose, CA
    EASY APPLY
    NEW
    14nm FinFET design processes Able to work in a team environment with other MaskDesigners and DesignEngineer's Needs to have… The Layout Designer will be responsible for physical design of RF and Analog circuits in a fast paced environment. Minimum expectations…
  • 3.6
    Peregrine Semiconductor – San Diego, CA
    6 days ago 6d
    Job Description: The Senior Mask tooling designer serves as the interface between the designengineer and the Fab. This individual… Responsible for engineering and production tapeouts to Peregrine’s external foundries. • Interfacing with mask houses and foundries…
  • 3.6
    Qualcomm – San Diego, CA
    Est. Salary $65k-$91k
    9 days ago 9d
    Job Id E1957081 Job Title Mask Layout Design Post Date 07/17/2017 Company Division Qualcomm Technologies… conjuction with circuit designers while using Cadence Virtuoso tool suite as well as verifying those designs using Calibre verification…
  • 3.1
    WAVSYS – San Jose, CA
    NEW
    14nm FinFET design processes Able to work in a team environment with other MaskDesigners and DesignEngineer's Needs to have… Description RF Analog Mask Layout Designer Job Overview: The Layout Designer will be responsible for physical design of RF and Analog…
  • 4.0
    Linear Technology – Milpitas, CA
    7 days ago 7d
    Linear Technology, part of Analog Devices, is seeking a MaskDesign Specialist in our Milpitas, CA facility. This position is… college grad who is looking for a mentorship or an experienced MaskDesigner with a solid 6-7 years of experience. Responsibilities…
  • 3.6
    Qualcomm – San Diego, CA
    Est. Salary $65k-$91k
    23 days ago 23d
    Job Id E1955412 Job Title Mask Layout Designer Post Date 05/08/2017 Company - Division Qualcomm… with the engineeringdesign team to understand design concepts, constraints, and milestones - Develop layout project schedules…
  • Novus Resources – San Diego, CA
    EASY APPLY
    Est. Salary $37k-$55k
    26 days ago 26d
    Novus' client is seeking experienced Mask Layout Designers to fulfill both block and project lead level roles working in a very… on experience and expertise. The layout designer will be responsible for physical design of RF and analog circuits in a fast paced…
  • 4.0
    Mentor Graphics – Fremont, CA
    Est. Salary $114k-$160k
    7 days ago 7d
    software engineer to work in the Mask Synthesis team in the Calibre business unit. You will be responsible for designing, developing… Development Engineer - Mask Synthesis - 6030 Job Location: US – CA – Fremont Job Category: R&D/Software Engineering Job Duties…
  • 3.3
    Alten Calsoft Labs – San Diego, CA
    EASY APPLY
    Est. Salary $38k-$55k
    26 days ago 26d
    part of a larger design team. -Must demonstrate proficiency in block level floorplanning, understanding of design rules, device matching… within a team Education: Required: Associate's, Electrical Engineering or equivalent experience Additional Information All…
  • 4.0
    Mentor Graphics – Fremont, CA
    Est. Salary $114k-$160k
    20 days ago 20d
    software engineer to work in the Mask Synthesis team in the Calibre business unit. You will be responsible for designing, developing… Development EngineerMask Synthesis - 5971 Job Location: US – CA – Fremont Job Category: R&D/Software Engineering Job Duties…
  • 3.0
    PROMEDIA TELECOM – San Jose, CA
    NEW
    14nm FinFET design processes ++Able to work in a team environment with other MaskDesigners and DesignEngineer's ++Needs… to 10 years experience in RF/analog layout Design ++Candidates need MaskDesigners with 14nm FinFET background. ++Custom layout…
  • 3.0
    Crossbar Inc. – Santa Clara, CA
    30 days ago 30d+
    Job Description Mask layout designengineer. RESPONSIBILITIES: Drawing layout of analog and mixed signal cells including… MINIMUM REQUIREMENTS: At least 2+ years of relevant maskdesign / layout experience. Experience using CAD/CAE tools such…
  • 3.6
    Qualcomm – San Diego, CA
    29 days ago 29d
    Job Id E1948812 Job Title RF/Analog Mask Layout Designer Post Date 03/20/2017 Company - Division… is seeking experienced mask layout designers to fulfill both large block level and project lead level roles working in a very…
  • 3.7
    Intel – Santa Clara, CA
    Est. Salary $98k-$135k
    12 days ago 12d
    Job Description Mask/OPC Development Engineer Description The Intel NVM (Non Volatile Memory) Process Technology Development… multiple other groups like Process Integration, Design Rules, CAD, Layout, Scribe and Mask shops Drive projects across multi-disciplinary…
  • 3.5
    Technosoft Corporation – New York, NY
    8 days ago 8d
    WRT Data Masking 2) Evaluate different DM tools and provide recommendation 3) Define architectural solution and design for DM… Start: ASAP The candidate should be an expert on Data masking, especially with Informatica DM tool and should have experience…
  • 3.6
    Qualcomm – San Diego, CA
    14 days ago 14d
    Job Id E1954902 Job Title Senior Mask Layout Designer - Power Management (San Diego, CA) Post Date 04/17/2017… with off-site design teams are also essential. Preferred Qualifications Bachelor's degree in electrical engineering preferred.…
  • 3.2
    Inphenix – Livermore, CA
    EASY APPLY
    Est. Salary $47k-$65k
    23 days ago 23d
    Work with team of process development and engineering to define fabrication process, mask layout, process flow, and test requirements… Description: The Device DesignEngineer is responsible for the design, development, and validation of optoelectronic products…
  • 3.4
    Oracle – United States
    Est. Salary $87k-$129k
    28 days ago 28d
    Redaction, Transparent Data Encryption, Key Management, Data Masking, Label Security, and Audit Vault and Database Firewall. We… on-premise and cloud-based sensitive data discovery and data masking products ·Work with product team to develop user stories…
  • 3.6
    Amazon – Austin, TX
    Est. Salary $93k-$125k
    26 days ago 26d
    nodes and ensure that the circuits meet timing checks, pass mask verification checks, power integrity checks, and reliability… Synthesis, Power Analysis, Power Integrity, Reliability, and Mask Verification) · Coding skills in Verilog and scripting languages…
  • 3.4
    Micron – Boise, ID
    NEW
    Support design rule checking (DRC) of both base and mask layers and interface Define algorithms for generation of mask data from… layout and mask generated data Successful candidates for this position will have: Excellent understanding of design rules…
  • 3.7
    Eagle Investment Systems – Wellesley, MA
    EASY APPLY
    Est. Salary $106k-$149k
    23 days ago 23d
    deduplication and compression). Experience with SAN zoning, LUN masking, Storage array configuration, I/O tuning and troubleshooting… Site Reliability DevOps Storage Engineer IV Candidates must have strong verbal and written communication skills and put client…
  • 3.5
    SRI International – Princeton, NJ
    Est. Salary $89k-$125k
    28 days ago 28d
    and maskdesign, device evaluation and characterization Working with wafer fabrication and process integration engineers to develop… Analog DesignEngineer Location(s) Princeton, NJ Employment Status Full Time Job Description An Analog Design Engineer…
  • 3.5
    Panasonic Corporation of North America – Marlborough, MA
    Est. Salary $61k-$84k
    NEW
    MATLAB programing skills are a plus Demonstrated expertise in maskdesign and tapeout procedures Excellent oral and written communication… for a Sr. MEMS DesignEngineer. What You’ll Get to Do: Key Accountabilities: 50% MEMS sensor design and simulation…
  • 2.7
    GLOBALFOUNDRIES – Essex, VT
    Est. Salary $100k-$132k
    NEW
    automation concerns, and resolve technical issues related to design tapeouts, mask build, and early user hardware. Candidate must be able… Product Engineering knowledge ​highly ​ preferred Understand product life cycle and work through all stages of design release…
  • 2.7
    GLOBALFOUNDRIES – East Fishkill, NY
    Est. Salary $78k-$112k
    NEW
    highly motivated engineer to work in the Tapeout and Testsite Organization as a Frame Design/Layout Engineer. You will be responsible… such as Field Application Engineering, Product Engineering, Release Team, Technology Development, Design Enablement, Process Integration…
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