ASIC Design Verification Engineer Jobs in Milpitas, CA | Glassdoor
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ASIC Design Verification Engineer Jobs in Milpitas, CA

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  • 4.5
    Technology Search International – Santa Clara, CA
    Est. Salary $91k-$116k
    7 days ago 7d
    Opportunity for an experienced ASICVerificationEngineer who has experience with SoCs and ASICs and verifying data center & communication… fantastic highly programmable ASICs. Requirements: 8+ years of ASIC / SoC Verification experience with SV/UVM environments…
  • 4.4
    VeriSilicon Holdings Co., Ltd. – San Jose, CA
    EASY APPLY
    Est. Salary $89k-$119k
    NEW
    familiar with all stages of the ASICdesign flow (including specification, architecture, and design implementation) Highly motivated… Verilog), and verification. Expected skills: 5+ years hands-on experience with focus on front-end complex RTL design Programming…
  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $112k-$152k
    NEW
    Experience in high-performance ASICverification. Good understanding of ASICdesign and verification methodologies and flows.… collaboration with design, software and hardware teams to ensure a successful product delivery. Mentor and enable other engineers.…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $98k-$122k
    24 days ago 24d
    interacting with designengineers to identify important verification scenarios. Create a constrained-random verification environment… with designengineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $140k-$188k
    4 days ago 4d
    for a Senior ASICVerificationEngineer: NVIDIA is seeking an elite ASICVerificationEngineer to verify the design and implementation… working on verifying ASICdesign using advanced verification methodologies. You are expected to understand the design and verify correctness…
  • 3.1
    Aquantia – San Jose, CA
    EASY APPLY
    Est. Salary $79k-$100k
    21 days ago 21d
    understanding of digital designverification methodologies and tools including: • Expertise in creating verification infrastructure using… Responsibilities: • Responsible to define and implement verification architectures for mixed signal data communications semiconductors…
  • 3.8
    Marvell Technology – Santa Clara, CA
    18 days ago 18d
    years of experience with digital ASICdesign, required. - Hands on experience with SOC verification using UVM and C. - Experience… functionality of designs and developing corresponding verification plans. Designing and developing components of our verification environment…
  • 4.4
    Embedded Resource Group – Mountain View, CA
    22 days ago 22d
    ASIC/FPGA DesignVerificationEngineer Seeking designverificationengineer for verification of FPGA design.… Job Requirements Required Skills: ASIC or FPGA designverification At least 2 + UVM projects in past System Verilog…
  • 3.2
    Rambus – Sunnyvale, CA
    Est. Salary $101k-$138k
    NEW
    teams including ASICdesignengineers and architects, other verificationengineers and system test engineers, security experts… Design and implement verification test plans, testbenches, infrastructure and platforms Work with ASICdesigners and architects…
  • Career Brokers, Inc. – San Jose, CA
    Est. Salary $120k-$185k
    8 days ago 8d
    The group requires a ASICverificationengineer with extensive experience on networking ASICverification, with in-depth knowledge… functioning silicon. You will be part of a verification team responsible of delivering ASICs for complex networking systems. You will…
  • 3.2
    Seagate Technology – Fremont, CA
    Est. Salary $93k-$126k
    11 days ago 11d
    Experience with advance ASICdesignverification methodology such as UVM and VMM flow. Experience with all popular ASIC EDA tools like… solutions innovation, seeks a Design and VerificationEngineer for an exciting role at our new Freemont Design Center. You will help us…
  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $103k-$143k
    NEW
    1208196 New Title: ASIC Physical DesignEngineer Location: San Jose, CA WHO YOU'LL WORK WITH… creative and talented team as Physical Design lead in San Jose, CA. You will work with ASIC Front-end teams to understand chip architecture…
  • 2.8
    cPacket Networks – San Jose, CA
    Est. Salary $81k-$112k
    4 days ago 4d
    troubleshoot issues in the design. This role may also require creating behavioral models of the design and developing RTL which… candidates to develop and integrate the current and future RTL designs into a UVM environment. Candidates will need to create reports…
  • 3.9
    Axelon, Inc. – San Jose, CA
    Est. Salary $98k-$134k
    NEW
    We are currently looking for a Senior ASIC/SoC VerificationEngineer (Contract Position) to join our team in San Jose, CA. He… and compute ASIC/ FPGA and system solutions. The ideal candidate must have prior experience developing Verification architecture…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $140k-$188k
    4 days ago 4d
    for a Senior ASICVerificationEngineer: NVIDIA is seeking elite ASICVerificationEngineers to verify the design and implementation… responsible for verification of the ASICdesign, architecture, golden models and micro-architecture using advanced verification methodologies…
  • 3.8
    Infinera – Sunnyvale, CA
    Est. Salary $136k-$174k
    5 days ago 5d
    impact on internal designs and architecture. Micro-architecture and design of ASIC/FPGA: Includes design documentation, review… of experience in ASICDesign. Participation in at least 1 full ASIC cycle as a designer from Arch to Bringup Good knowledge and…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    Est. Salary $111k-$151k
    4 days ago 4d
    Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business… technical oversight. Basic Qualifications FPGA & ASICVerification experience. Language Proficient in VHDL/Verilog for…
  • 2.9
    Toshiba America Electronic Components – San Jose, CA
    EASY APPLY
    Est. Salary $127k-$171k
    22 days ago 22d
    leader of the Storage Research and Design Center SoC development team, the Director, ASICverification is responsible for creating innovative… architecture(s) and new ASICdesign(s) with functional verification and validation as part of the primary task. The candidate will mentor…
  • 4.2
    Quanergy – Sunnyvale, CA
    Est. Salary $81k-$106k
    NEW
    Digital ASICDesignEngineer-17040008 Location: Sunnyvale, California, United States Full-time The Digital ASIC Design… characterize/test the performance of the designedASIC, and work to integrate the design into our LiDAR sensors. A successful…
  • 3.8
    Marvell Technology – Santa Clara, CA
    Est. Salary $93k-$118k
    18 days ago 18d
    closure. * MS in EE with 3 years of work experience in SOC/ASIC/IP development. * Must have knowledge and experience of HDL… Knowledge of UVM and System Verilog is required. * Background in ASIC implementation including lint, CDC, synthesis, formal and static…
  • 3.7
    Intel Corporation – San Jose, CA
    Est. Salary $90k-$116k
    15 days ago 15d
    Experienced Hire ASICDesignEngineer Job Description Component DesignEngineers are responsible for the design and development… cross-functioning with IP teamsStrong understanding of hardware design, designverification, timing analysis, clock domain crossing, and lintProficient…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $110k-$152k
    11 days ago 11d
    Architecture, Designverification, Physical Design, DFT, and power teams to achieve first tapeout success on designs 3) Develop… aspects of development design for large SOC blocks including: Internal and external IP integration, design of system bus and control…
  • 3.6
    Fortinet – Sunnyvale, CA
    Est. Salary $87k-$114k
    15 days ago 15d
    Description Fortinet ASICdesign team is looking for a top computer engineering or electrical engineering graduate with an interest… member of the ASICdesign team, you will help design Fortinet’s next generation Network Processor and System-On-Chip ASIC to accelerate…
  • ASICSoft, Inc. – Milpitas, CA
    23 days ago 23d
    8-12+ years ASICDesignVerification Expert SystemVerilog Coding Strong UVM, OVM FPGA Bring-up Experience with PHY…
  • 3.7
    Intel Corporation – San Jose, CA
    Est. Salary $99k-$124k
    NEW
    Verification Engineer Job Description Intel (PSG) is looking for an experienced DesignVerificationEngineer to verify PCIe… Electrical Engineering, Computer Engineering, or equivalent with a minimum of 5+ years of experience verifying complex ASICs Strong…
  • 2.9
    Toshiba America Electronic Components – San Jose, CA
    EASY APPLY
    Est. Salary $92k-$125k
    22 days ago 22d
    will own the whole or parts of sub modules verification and/or full chip verification in SSD controllers. Such modules are SATA… controllers. Define and develop verification architecture and methodology Writing verification plans, tests, and building random…
  • 3.9
    Cisco Systems – San Jose, CA
    NEW
    the ability to design and debug with minimal oversight. You are an ASICDesign for Test engineer with 10+ years… talented team as Design for Test lead in San Jose, CA. You will work with ASIC Front-end RTL teams, backend physical design teams to understand…
  • 2.9
    Toshiba America Electronic Components – San Jose, CA
    EASY APPLY
    Est. Salary $126k-$169k
    22 days ago 22d
    and Linux environments Other: 7+ years of SoC/ASICverification experience Hands on experience using UVM SSD controller… activity will involve the development of a verification plan, in collaboration with the design and architecture teams, the definition…
  • 1.0
    Asquare, Inc – Onizuka AFB, CA
    9 days ago 9d
    hand-on experience from industry ASICdesign flow including RTL coding, debugging/verification, and supporting synthesis and timing… Job Title: ASIC/RTL DesignEngineer Location: Sunnyvale, CA Job Code: JP00000777 Duration: 6 months contract (with possibility…
  • 4.4
    Quantenna Communications – Fremont, CA
    25 days ago 25d
    Quantenna’s PHY ASICverification. Take full responsibility for a Block Verification. Actively Interactive with design team for Debug… for details Functional Verification. Execute and maintain regressions. Work closely with ASICdesign and systems team to execute…
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