ASIC Design and Verification Engineer Jobs in San Jose, CA | Glassdoor
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ASIC Design and Verification Engineer Jobs in San Jose, CA

256 Jobs

  • 4.4
    VeriSilicon Holdings Co., Ltd. – San Jose, CA
    EASY APPLY
    $90k-$119k(Glassdoor est.)
    HOT
    familiar with all stages of the ASICdesign flow (including specification, architecture, and design implementation) Highly motivated… Verilog), and verification. Expected skills: 5+ years hands-on experience with focus on front-end complex RTL design Programming…
  • 4.4
    Embedded Resource Group – Mountain View, CA
    NEW
    ASIC/FPGA DesignVerificationEngineer Seeking designverificationengineer for verification of FPGA design.… Job Requirements Required Skills: ASIC or FPGA designverification At least 2 + UVM projects in past System Verilog…
  • 4.4
    Google – Mountain View, CA
    $97k-$122k(Glassdoor est.)
    7 days ago 7d
    interacting with designengineers to identify important verification scenarios. Create a constrained-random verification environment… with designengineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes…
  • 3.2
    Aquantia – San Jose, CA
    EASY APPLY
    $83k-$104k(Glassdoor est.)
    NEW
    understanding of digital designverification methodologies and tools including: • Expertise in creating verification infrastructure using… Responsibilities: • Responsible to define and implement verification architectures for mixed signal data communications semiconductors…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    $106k-$144k(Glassdoor est.)
    NEW
    the SSD Controller ASICverification methodology and environment development Detailed module verification test plan, covering… chip level verification Validate SoC design in FPGA prototyping and emulation platforms Work closely with FW engineers to resolve…
  • 3.8
    Marvell Technology – Santa Clara, CA
    $87k-$110k(Glassdoor est.)
    1 days ago 1d
    micro-architecture Implement RTL design in Verilog, Lint check and module level verification Create design documentation, programming… programming guide to software engineers or customers Support verification effort at chip level Support IP integration with SOC…
  • 4.4
    NVIDIA – Santa Clara, CA
    $141k-$189k(Glassdoor est.)
    NEW
    for a Senior ASICVerificationEngineer: NVIDIA is seeking elite ASICVerificationEngineers to verify the design and implementation… responsible for verification of the ASICdesign, architecture, golden models and micro-architecture using advanced verification methodologies…
  • 3.9
    Cisco Systems – San Jose, CA
    $113k-$153k(Glassdoor est.)
    HOT
    Experience in high-performance ASICverification. Good understanding of ASICdesign and verification methodologies and flows.… collaboration with design, software and hardware teams to ensure a successful product delivery. Mentor and enable other engineers. Skills…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    EASY APPLY
    $94k-$129k(Glassdoor est.)
    NEW
    and deployment of the verification methodology Requirements: 3+ years of SoC/ASICverification experience Hands on… integration in the verification platform Definition of the verification plan in collaboration with the design and architecture…
  • 3.1
    Hermes-Microvision, Inc. – San Jose, CA
    $61k-$78k(Glassdoor est.)
    Today 4hr
    the following opening: Digital IC DesignEngineer (ASIC) Work with partners on the design process of the digital components… experiences, in electrical engineering. Hands-on experiences of analog IC design, layout, verification, tape out, and testing. Familiar…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    EASY APPLY
    $114k-$155k(Glassdoor est.)
    NEW
    Requirements: 7+ years of SoC/ASICverification experience Hands on experience using UVM SSD controller experience is preferred… activity will involve the development of a verification plan, in collaboration with the design and architecture teams, the definition…
  • 3.1
    Hermes-Microvision – San Jose, CA
    EASY APPLY
    $83k-$111k(Glassdoor est.)
    Today 6hr
    experiences, in electrical engineering. Hands-on experiences of analog IC design, layout, verification, tape out, and testing. Familiar… level verification of the designs. Work closely with the partner to conduct function / performance tests and verification after…
  • 4.4
    NVIDIA – Santa Clara, CA
    $141k-$189k(Glassdoor est.)
    NEW
    for a Senior ASICVerificationEngineer: NVIDIA is seeking an elite ASICVerificationEngineer to verify the design and implementation… working on verifying ASICdesign using advanced verification methodologies. You are expected to understand the design and verify its…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    $95k-$129k(Glassdoor est.)
    NEW
    with designengineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes… Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers…
  • 3.9
    Cisco Systems – San Jose, CA
    $106k-$148k(Glassdoor est.)
    HOT
    Title: ASIC Physical DesignEngineer Location: San Jose, CA WHO YOU'LL WORK WITH: Our creative and talented team as Physical… Physical Design lead in San Jose, CA. You will work with ASIC Front-end teams to understand chip architecture and drive physical…
  • 3.7
    Quanergy – Sunnyvale, CA
    $84k-$107k(Glassdoor est.)
    1 days ago 14hr
    UVM-based verification environment. She/He will be a leader for verification efforts at the module and chip-level for both ASIC and… The Senior DesignVerificationEngineer at Quanergy will be responsible for collaboratively developing and maintaining portions…
  • 3.7
    LAUNCH, Technical Workforce Solutions – Sunnyvale, CA
    1 days ago 21hr
    Experience with modern verification methodologies, including UVM and/or OVM Experience in developing FPGAs and/or ASICs for high-reliability… LAUNCH Technical Workforce Solutions is seeking FPGA Design/VerificationEngineers for an opportunity in Sunnyvale, CA. Job Duties…
  • 3.8
    Marvell Technology – Santa Clara, CA
    $94k-$119k(Glassdoor est.)
    26 days ago 26d
    closure. MS in EE with 3 years of work experience in SOC/ASIC/IP development. Must have knowledge and experience of HDL in… Knowledge of UVM and System Verilog is required. Background in ASIC implementation including lint, CDC, synthesis, formal and static…
  • 4.4
    Google – Mountain View, CA
    $97k-$122k(Glassdoor est.)
    11 days ago 11d
    technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's… cache, DRAM, power management or security. Experience with verification in a standard environment such as UVM. Experience with…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    1 days ago 23hr
    SSD controller H/W architecture & design Strong Experience in RTL design, designverification, synthesis & formality Solid experience… implementation, synthesis & formality check Candidate to support DesignVerification & FPGA Validation, teams Investigate controller requirements…
  • 4.0
    Mentor Graphics – Fremont, CA
    $97k-$133k(Glassdoor est.)
    Today 10hr
    understanding of ASIC & FPGA Design and Verification flow is required. Strong knowledge of Advanced Verification methodologies… Functional Verification products in North America accounts. The Functional Verification Senior Applications Engineer will be…
  • 3.8
    Marvell Technology – Santa Clara, CA
    $87k-$110k(Glassdoor est.)
    4 days ago 4d
    analog circuits. Perform RTL, pre- and post-layout verification of designs on block and system levels using simulation software… multiple clock domain design concept Experience in developing test benches for functional verification and RTL debugging Preferred…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    $135k-$173k(Glassdoor est.)
    1 days ago 1d
    architects in developing a design specification, and they will be responsible for the design, and verification/implementation of the… closely with other design team members in SoC integration and chip level verification and timing Port designs into FPGA prototyping…
  • 4.4
    Quantenna Communications – Fremont, CA
    EASY APPLY
    5 days ago 5d
    Quantenna’s PHY ASICverification. Take full responsibility for a Block Verification. Actively Interactive with design team for Debug… for details Functional Verification. Execute and maintain regressions. Work closely with ASICdesign and systems team to execute…
  • 3.5
    Cavium – San Jose, CA
    $93k-$129k(Glassdoor est.)
    NEW
    UVM. Responsibilities: Contribute as an ASICVerificationEngineer developing the next generation of cloud, networking… directly with senior members of the ASIC team to develop comprehensive, state of the art, verification environment using the latest methodology…
  • 3.6
    Broadcom Corporation – San Jose, CA
    $120k-$152k(Glassdoor est.)
    7 days ago 7d
    years, equivalent experience in ASICdesign and verification. Experience in verifying designs at system level and block level… System Verilog Assertions. Strong experience in ASICdesignverification flows and DV methodologies. Networking domain knowledge…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    $139k-$178k(Glassdoor est.)
    1 days ago 1d
    Driving SoC's physical design implementation with ASIC vendor Working closely with Verification, Validation, & Firmware teams… leading the design team to define and develop Flash Controller H/W architecture(s) and new ASICdesign(s) with RTL design & implementation…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    $88k-$119k(Glassdoor est.)
    1 days ago 14hr
    Digital Processor ASIC/FPGA Designer: The ASIC/FPGA DesignEngineer will be working in the Optical Payloads Center of Excellence… development activities (ASIC). Knowledge of development of verification plans and approaches to support FPGA/ASIC development. Good…
  • Novus Resources – San Jose, CA
    EASY APPLY
    $72k-$100k(Glassdoor est.)
    5 days ago 5d
    experience in ASIC / SoC Verification Expert knowledge in UVM, which is an object-oriented Hardware verification language library… As a designverificationengineer you will work with a fast paced Integrated Wireless Technology (IEEE 802.11x, BT, and FM) team…
  • 3.9
    Cisco Systems – San Jose, CA
    $101k-$129k(Glassdoor est.)
    11 days ago 11d
    Experience in high-performance ASICverification. Good understanding of ASICdesign and verification methodologies and flows.… Participate in the architecture and verification of complex, high-performance, and highly integrated ASICs used in Cisco's networking products…
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