ASIC Design Engineer Jobs in San Jose, CA | Glassdoor
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ASIC Design Engineer Jobs in San Jose, CA

431 Jobs

  • 4.4
    VeriSilicon Holdings Co., Ltd. – San Jose, CA
    EASY APPLY
    $90k-$119k(Glassdoor est.)
    9 days ago 9d
    -end complex RTL design Programming skills in Verilog Must be familiar with all stages of the ASICdesign flow (including specification… of computer graphics and low-power design techniques a plus Experience of GPU shader design a plus…
  • 3.9
    Fortinet – Sunnyvale, CA
    $105k-$137k(Glassdoor est.)
    21 days ago 21d
    top-notch ASICengineer to join our front end design team. The team is responsible for designing Fortinet’s next generation ASICs accelerating… Educational Requirement BS or MS in Electrical Engineering with 2+ years of relevant work experience. #LI-EL1…
  • 4.4
    NVIDIA – Santa Clara, CA
    $99k-$130k(Glassdoor est.)
    14 days ago 14d
    collaborating with other architects, ASICdesigners and verification engineers to design high frequency clocks. You should be… today. The GPU clocks group is looking for a top-notch ASICengineer to join the team. The Team is responsible for crafting all…
  • 3.9
    Cisco Systems – San Jose, CA
    $106k-$148k(Glassdoor est.)
    9 days ago 9d
    Title: ASIC Physical DesignEngineer Location: San Jose, CA WHO YOU'LL WORK WITH: Our creative and talented team as Physical… Physical Design lead in San Jose, CA. You will work with ASIC Front-end teams to understand chip architecture and drive physical…
  • ASICSoft, Inc. – San Jose, CA
    19 days ago 19d
    7-10+ years ASICDesign Strong RTL Design with SystemVerilog Experienced with Synthesis and Timing Closure FPGA Lab…
  • 3.9
    Ambarella – Santa Clara, CA
    $70k-$91k(Glassdoor est.)
    7 days ago 7d
    Electrical Engineering with 0-5 years of experience. Good understanding of computer architecture, logic design and VLSI design. Knowledge… micro-architecture specifications for a next generation media processor. Designing and implementing video compression logic, image processing…
  • 3.7
    Intel – San Jose, CA
    $91k-$118k(Glassdoor est.)
    24 days ago 24d
    Job Description Component DesignEngineers are responsible for the design and development of electronic components. Responsibilities… Responsibilities may include: the design of chip layout circuit design, circuit checking, device evaluation and characterization, documentation…
  • 4.0
    ASML – San Jose, CA
    $101k-$126k(Glassdoor est.)
    17 days ago 17d
    applications? We are looking for a digital IC designengineer to be responsible for engineering of analog and digital components of the… with partners on the design process of the digital components. Together with the designengineering team from the partners…
  • 3.8
    Marvell Technology – Santa Clara, CA
    $87k-$110k(Glassdoor est.)
    15 days ago 15d
    control, supporting P&R, design rule checks RTL design and give design review. Work with testing engineer to evaluate, validate and… Responsible for design, development, modification and evaluation of high-speed digital circuit for signal processing components…
  • 4.4
    Google – Mountain View, CA
    $97k-$122k(Glassdoor est.)
    NEW
    complex digital design blocks by fully understanding the design specification and interacting with designengineers to identify important… and corner-cases. Debug tests with designengineers to deliver functionally correct design blocks. Close coverage measures to…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    EASY APPLY
    $94k-$129k(Glassdoor est.)
    NEW
    verification methodology Requirements: 3+ years of SoC/ASIC verification experience Hands on experience using UVM SSD… development of a verification plan, in collaboration with the design and architecture teams, the definition and implementation of…
  • 3.8
    Marvell Technology – Santa Clara, CA
    $87k-$110k(Glassdoor est.)
    NEW
    Qualification: A BS, MS or PhD in Electrical or Computer Engineering or similar discipline Experience in behavioral and RTL… circuits. Perform RTL, pre- and post-layout verification of designs on block and system levels using simulation software. Execute…
  • 4.0
    Apple – Santa Clara, CA
    $121k-$164k(Glassdoor est.)
    Today 6hr
    Analog ASICDesignEngineer - CSM Job Number: 113051437 Santa Clara Valley, California, United States Posted: Sep. 21, 2017… subsystem development groups and internal/external ASIC development engineering teams to ensure proper specifications, documentation…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    $93k-$120k(Glassdoor est.)
    NEW
    Participating in the design of SSD controllers/SoC Implementing and delivering RTL Assisting in synthesis and gate-level…
  • 3.7
    Infinera – Sunnyvale, CA
    $106k-$137k(Glassdoor est.)
    13 days ago 13d
    ASICDesignEngineer (Infinera Corporation – Sunnyvale, CA) Responsible for post-silicon validation, troubleshooting and debugging… application-specific integrated circuits (ASICs). Engage in PVT characterization of test-chips and production ASICs. Create silicon validation…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    $135k-$173k(Glassdoor est.)
    NEW
    supporting ASIC, FPGA and Palladium platforms SoC level DFT and test structures for ATE working closely with ASIC Vendor Work… Responsibilities: Participate in the SSD Controller ASIC HW & FW specification development SoC top level integration…
  • 3.7
    Quanergy – Sunnyvale, CA
    $84k-$110k(Glassdoor est.)
    8 days ago 8d
    Digital ASICDesignEngineer-17040008 Location: Sunnyvale, California, United States Full-time The Digital ASIC Design… characterize/test the performance of the designedASIC, and work to integrate the design into our LiDAR sensors. A successful…
  • 3.8
    Marvell Technology – Santa Clara, CA
    $83k-$111k(Glassdoor est.)
    24 days ago 24d
    stages of ASICdesign flows, and is experienced with state-of-the-art design tools. The candidate is strong in logic design and verification… Provide design documentation, description and information to application engineers, field application engineers, test engineers, production…
  • Online Technical Services – San Jose, CA
    21 days ago 21d
    Job Description Digital IC DesignEngineer (ASIC) San Jose, California, United States · EE (Digital) · RA13 DESCRIPTION… Work with partners on the design process of the digital components. Together with the designengineering team from the partners,…
  • 3.7
    Intel – San Jose, CA
    $94k-$130k(Glassdoor est.)
    NEW
    working on complex ASIC and FPGA designs in leading edge process nodes.Responsibilities include the following:* Design and integration… in electrical engineering or computer science* 4+ years of experience in high performance digital logic designs and integration…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    $139k-$178k(Glassdoor est.)
    NEW
    leader of the Storage Research and Design Center SoC development team, the Director, ASICdesign is responsible for creating innovative… architecture(s) and new ASICdesign(s) with RTL design & implementation as part of the primary task. The candidate will work closely…
  • 3.9
    Cisco Systems – San Jose, CA
    $113k-$153k(Glassdoor est.)
    9 days ago 9d
    Experience in high-performance ASIC verification. Good understanding of ASICdesign and verification methodologies and flows… collaboration with design, software and hardware teams to ensure a successful product delivery. Mentor and enable other engineers. Skills…
  • 3.5
    Cavium – San Jose, CA
    $90k-$117k(Glassdoor est.)
    Today 4hr
    You will work directly with senior members of the ASIC team to learn and design state of art high speed digital systems. Responsibilities… As a new graduate engineer, you would contribute as a designengineer developing the next-generation of multi-core processors.…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    $88k-$119k(Glassdoor est.)
    NEW
    Digital Processor ASIC/FPGA Designer: The Staff ASIC/FPGA DesignEngineer will be working in the RF Center of Excellence (RF… effort to meet the customer requirements. The Staff FPGA/ASICdesigner will provide technical support across the enterprise as…
  • 3.9
    APN Software Services Inc. – San Jose, CA
    20 days ago 20d
    Job Title Analog IC DesignEngineer (ASIC) Location: 1762 Automation Parkway, San Jose, CA 95131 Length - Permanent job… the design process of the analog components. Together with the designengineering team from the partners, identify design solutions…
  • 3.1
    Hermes-Microvision – San Jose, CA
    EASY APPLY
    $83k-$111k(Glassdoor est.)
    27 days ago 27d
    the design process of the analog components. Together with the designengineering team from the partners, identify design solutions… hands-on experiences, in electrical engineering. Hands-on experiences of analog IC design, layout, verification, tape out, and…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    $93k-$120k(Glassdoor est.)
    24 days ago 24d
    Descriptions: The ASICDesignEngineer will be working on the leading edge SSD controller IP design from architecture to production… support physical design and system level analysis. Qualifications: BS, MS, or PhD in Electrical Engineering with 5-10 years…
  • 3.7
    Intel – San Jose, CA
    $101k-$143k(Glassdoor est.)
    14 days ago 14d
    Job Description As a member of the ASIC Frontend Design and Integration team, you will be part of Intel's Programmable Solution… Solution Group PSG, working on complex ASIC and FPGA designs in leading edge process nodes. Responsibilities include the following…
  • 3.9
    Cisco Systems – San Jose, CA
    $101k-$149k(Glassdoor est.)
    NEW
    knowledge -Network ASICdesign, IPS, foundries / wafer fabrication, packaging and integration, Product HW Design is preferred -Technical… You'll influence both technology and business for leading edge ASICdesign, integration and packaging business and market needs. You…
  • 3.7
    Xilinx – San Jose, CA
    $126k-$167k(Glassdoor est.)
    Today 11hr
    optimizations, logic optimization and technology mapping algorithms for ASIC or FPGA synthesis tools is desirable. Hands on experience… solvers and timing analysis engines is desirable. Strong background in basic digital design principles, graph theory and…
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