ASIC Physical Design Engineer Jobs in San Jose, CA | Glassdoor
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ASIC Physical Design Engineer Jobs in San Jose, CA

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  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $104k-$144k
    NEW
    Title: ASICPhysicalDesignEngineer Location: San Jose, CA WHO YOU'LL WORK WITH: Our creative and talented team as Physical… through physical synthesis and Place & Route tools and working with ASIC vendors. As member of physical/implementation design team…
  • 3.1
    Toshiba – San Jose, CA
    Est. Salary $134k-$172k
    13 days ago 13d
    3rd party IPs for SoC integation Drive SoC physicaldesign implementation with ASIC vendor Work closely with Verification, Validation… SATA SSD technologies prior to design. Will drive the development of the SSD Controller ASICdesign specification. Perform analysis…
  • Approgence – San Jose, CA
    Est. Salary $75k-$107k
    8 days ago 8d
    Job Title : ASICPhysicalDesignEngineer Job Location : San Diego & San Jose, CA Job Description : This person will… complete physicaldesign. He will identify physicaldesign issues in early stage, working with RTL engineer to fix. He will isolate…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $110k-$154k
    10 days ago 10d
    Architecture, Design verification, PhysicalDesign, DFT, and power teams to achieve first tapeout success on designs 3) Develop… aspects of development design for large SOC blocks including: Internal and external IP integration, design of system bus and control…
  • 2.9
    Toshiba America Electronic Components – San Jose, CA
    EASY APPLY
    Est. Salary $138k-$178k
    8 days ago 8d
    party IP's for SoC integation Drive SoC physicaldesign implementation with ASIC vendor Work closely with Verification, Validation… experience working with ASIC vendors or internal COT flow for physical implementation Must have experience in ASIC vendor management…
  • Fujitsu Network Communications – Sunnyvale, CA
    17 days ago 17d
    Design for ASIC using Socionext Advanced Standard Cell technology. The Staff PhysicalDesignEngineer will have opportunities to work… MSEE preferred. Experience in ASIC/COT design flow. Experience in PhysicalDesign Implementation which includes Floorplan…
  • 3.9
    Cisco Systems – San Jose, CA
    NEW
    ability to design and debug with minimal oversight. "Who You Are" You are an ASICDesign for Test engineer with 10+ years… work with ASIC Front-end RTL teams, backend physicaldesign teams to understand chip architecture and drive design for test requirements…
  • 3.7
    Intel – San Jose, CA
    Est. Salary $93k-$138k
    7 days ago 7d
    Job Description As a member of the ASIC Frontend Design and Integration team, you will be part of Intel's Programmable Solution… Solution Group PSG, working on complex ASIC and FPGA designs in leading edge process nodes. Responsibilities include the following:…
  • 2.9
    Toshiba America Electronic Components – San Jose, CA
    EASY APPLY
    Est. Salary $135k-$173k
    14 days ago 14d
    supporting ASIC, FPGA and Palladium platforms SoC level DFT and test structures for ATE working closely with ASIC Vendor Work… Responsibilities: Participate in the SSD Controller ASIC HW & FW specification development SoC top level integration…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $99k-$130k
    7 days ago 7d
    collaborating with other architects, ASICdesigners and verification engineers to design high frequency clocks. You should be… today. The GPU clocks group is looking for a top-notch ASICengineer to join the team. The Team is responsible for crafting all…
  • 3.9
    Cisco Systems – San Jose, CA
    NEW
    Lead, ASICPhysicalDesign Location: San Jose, CA WHO YOU'LL WORK WITH: Our creative and talented team as Physical Design… will work with ASIC Front-end teams to understand chip architecture and drive physical aspects early in the design cycle, driving…
  • 3.3
    Sony Electronics – San Jose, CA
    Est. Salary $90k-$124k
    17 days ago 17d
    and design. Sony Electronics, a global leader in image sensors, is seeking a staff VLSI/ASIC logic DesignEngineer to work… then develop and implement solutions Familiarity with ASIC/SoC design/verification methodologies Ability to write detailed…
  • 3.4
    AMD – Sunnyvale, CA
    Est. Salary $88k-$120k
    NEW
    team is looking for a Logic DesignEngineer who has experience working on complex IP/SOC Designs from concept to post silicon.… plan review,and corner case brainstorm. Working with physicaldesign team to ensure timing and area closure, and meet DFT and…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    Est. Salary $92k-$119k
    17 days ago 17d
    Descriptions: The ASICDesignEngineer will be working on the leading edge SSD controller IP design from architecture to production… support physicaldesign and system level analysis. Qualifications: BS, MS, or PhD in Electrical Engineering with 5-10…
  • 3.4
    Tektronix – Santa Clara, CA
    Est. Salary $104k-$137k
    6 days ago 6d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • 3.4
    Advanced Micro Devices, Inc. – Sunnyvale, CA
    Est. Salary $104k-$141k
    5 days ago 5d
    relevant automation. Enable efficient support of multiple large engineering projects simultaneously Experience in development flows… collaboration skills. Experience working in large multi-site engineering organizations Demonstrated ability to work cross-functionally…
  • 4.0
    Roche – Santa Clara, CA
    Est. Salary $101k-$140k
    NEW
    years of experience as an ASICDesignEngineer . EDUCATION: Minimum BS in Electrical Engineering.… Architecture; knowledge and hands-on experience from industry ASICdesign flow including RTL coding, debugging/verification, and supporting…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $103k-$135k
    15 days ago 15d
    degree in Electrical Engineering or equivalent practical experience. Experience in software design and ASICdesign methodology development… installation/troubleshooting/debugging with vendors. As an ASICDesignEngineer on the chip implementation team, you will be responsible…
  • 3.7
    Xilinx – San Jose, CA
    Est. Salary $122k-$179k
    10 days ago 10d
    Familiar with state of the art placement/routing/physical synthesis algorithms for ASICs and/or FPGAs. Expert with C , data structures… software engineer to be part of the Xilinx Vivado Physical Implementation team. This team is responsible for design, implementation…
  • Approgence – San Jose, CA
    Est. Salary $85k-$114k
    8 days ago 8d
    perform bit-exact simulation. Modem ASICDesign team is working with physicaldesignengineer to deliver netlist, spec timing constraints… Job Title : Senior ASIC/ RTL DesignEngineer with DSP Job Location : San Diego & San Jose, CA Job Description : This…
  • 3.6
    Qualcomm – San Jose, CA
    Est. Salary $102k-$131k
    NEW
    Job Id E1957027 Job Title Low-power ASICDesignengineer - Wi-Fi IoT Post Date 08/03/2017 Company Division… silicon bringup/debug of ASICdesigns" id="hdnMinimumQualifications">- 3+ yrs Experience in low-power design. Hardware description…
  • 2.8
    GLOBALFOUNDRIES – Santa Clara, CA
    24 days ago 24d
    quality ASICdesigns Gather requirements and product specifications from synthesis, design for test, physicaldesign, and timing… utilizing CMOS cell-based ASIC technologies. Essential Responsibilities: Implementation of electronic design automation software…
  • 3.7
    Fortive – Santa Clara, CA
    Est. Salary $97k-$128k
    5 days ago 5d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • 3.9
    Nokia – Sunnyvale, CA
    Est. Salary $88k-$123k
    8 days ago 8d
    responsible for back-end ASICdesign including physical place and route, timing analysis and fixing, and physical verification. You will… communications! We are now looking for Senior Specialist, 5G ASICPhysicalDesign to join our team. Key responsibilities In this…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    Est. Salary $103k-$142k
    NEW
    Work with PhysicalDesign team to implement design Qualifications: BS, MS or PhD degree in Electrical Engineering or Computer… perform timing analysis Work with Design Verification and emulation team to validate design Develop functional models for architectural…
  • Yang Technical Solutions – San Jose, CA
    EASY APPLY
    22 days ago 22d
    PhysicalDesignEngineer Job Description: 5+ years of industry experience in physicaldesign implementation (placement… Compiler 1 is must. Needs to be familiar with all aspects of ASIC integration including floorplanning, clock and power distribution…
  • 3.0
    Fluke Corporation – Santa Clara, CA
    Est. Salary $88k-$117k
    5 days ago 5d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $109k-$148k
    5 days ago 5d
    As a PhysicalDesignEngineer, you will leverage your strong technical background to execute the back-end design of ASICs that… * Experience designing high-performance ASICs in advanced process nodes and with front-end design tools. * Experience interacting…
  • 3.4
    Advanced Micro Devices, Inc. – Sunnyvale, CA
    Est. Salary $102k-$139k
    24 days ago 24d
    KEY RESPONSIBILITIES Work in a team of design verification and designengineers, involved in all aspects of the verification… REQUIREMENTS Required: Bachelor's, Computer Engineering and/or Electrical Engineering #LI-PS1 Requisition Number: 37921…
  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $97k-$139k
    NEW
    such as DCBX/PFC, NIV/802.1BR, QoS, L2/L3 switching, forwarding ASICs, ACL, SPAN/ERSPAN, tunneling, L4-L7 networking protocols or… firmware development for networking/storage adapters, such as physical/MAC layer, NCSI, I2C/SMBus, BIOS/BMC interfaces, SAN/PXE/iSCSI…
  • 3.1
    Fujitsu – Sunnyvale, CA
    Est. Salary $66k-$92k
    NEW
    Design for ASIC using Socionext Advanced Standard Cell technology. The Staff PhysicalDesignEngineer will have opportunities to work… Experience with 5 or more Chip Designs Experience in ASIC/COT design flow. Experience in PhysicalDesign Implementation which…
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