Job Type
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ASIC Physical Design Engineer Jobs in San Jose, CA

92 Jobs

  • 3.2
    Aquantia – San Jose, CA
    EASY APPLY
    $111k-$163k(Glassdoor est.)
    28 days ago 28d
    of a scripting language like Python is a plus. Knowledge of ASIC and DSP software implementation, fixed point operation and lab… Multiple Positions/Levels: Communication System Engineer Responsibilities: Define the system requirements, develop digital…
  • 3.6
    Broadcom – Santa Clara, CA
    $109k-$140k(Glassdoor est.)
    15 days ago 15d
    networking ASIC is a plus. Working in SOC with frequencies more that 1GHz is an advantage. Work effectively with design verification… logic design methodology and to the continual improvement of critical methodology linkages to circuit, physicaldesign and design…
  • Approgence – Santa Clara, CA
    22 days ago 22d
    for a senior expert in SoC PhysicalDesign and RTL Delivery Management for advanced modem Baseband ASIC. Provide technical support… Job Title : SoC PhysicalDesign and RTL Delivery Lead / Principal Engineer Job Location : Santa Clara, CA Job Description…
  • 4.1
    Nokia – Sunnyvale, CA
    $90k-$126k(Glassdoor est.)
    15 days ago 15d
    responsible for back-end ASICdesign including physical place and route, timing analysis and fixing, and physical verification. You will… communications! We are now looking for Senior Specialist, 5G ASICPhysicalDesign to join our team. Key responsibilities In this…
  • 3.1
    Avago Technologies – Santa Clara, CA
    $104k-$137k(Glassdoor est.)
    15 days ago 15d
    networking ASIC is a plus. Working in SOC with frequencies more that 1GHz is an advantage. Work effectively with design verification… logic design methodology and to the continual improvement of critical methodology linkages to circuit, physicaldesign and design…
  • 2.7
    Global Foundries – Santa Clara, CA
    28 days ago 28d
    CMOS cell-based ASIC technologies. Essential Responsibilities: Implementation of electronic design integration and… tools (Cadence Innovus, Mentor Calibre) Familiar with ASIC SOC design integration and finishing flows Additional Eligibility…
  • 3.5
    Mobiveil – Milpitas, CA
    EASY APPLY
    $60k-$87k(Glassdoor est.)
    11 days ago 11d
    Experience in low power ASICdesign implementation, power simulation and analysis flow, and ASICphysicaldesign methodology Experience… concepts of power consumption, power estimation and low power design Good understanding of power considerations at architectural…
  • 3.1
    Fujitsu – Sunnyvale, CA
    $66k-$91k(Glassdoor est.)
    14 days ago 14d
    Design for ASIC using Socionext Advanced Standard Cell technology. The Staff PhysicalDesignEngineer will have opportunities to work… Experience with 5 or more Chip Designs Experience in ASIC/COT design flow. Experience in PhysicalDesign Implementation which…
  • 4.4
    NVIDIA – Santa Clara, CA
    $101k-$144k(Glassdoor est.)
    11 days ago 11d
    be doing: Drive physicaldesign and timing convergence of high-frequency low-power CPU, GPU, and/or ASIC at block level, cluster… and hands-on skills in RTL/Logic design for timing closure desired. Knowledge in physicaldesign and optimization e.g. placement…
  • 3.7
    Xilinx – San Jose, CA
    10 days ago 10d
    convolutional networks (DCNN) and the software or hardware (ASIC) realization of these algorithms is highly valuable for this… at least one of the following technologies: software, FPGA or ASIC. Skills – the candidate would have skills in several, but…
  • 3.7
    Xilinx – San Jose, CA
    $128k-$170k(Glassdoor est.)
    8 days ago 8d
    Familiar with state of the art placement/routing/physical synthesis algorithms for ASICs and/or FPGAs. Expert with C , data structures… software engineer to be part of the Xilinx Vivado Physical Implementation team. This team is responsible for design, implementation…
  • 3.1
    Avago Technologies – Sunnyvale, CA
    $104k-$137k(Glassdoor est.)
    22 days ago 22d
    verification, and of ASICdesign methodology Experience in one or more of the following areas is desired: mimo, ofdm, agc, channel… complex, highly integrated ASICs. Desired Skills and Qualifications: Typically a BS degree and 12 years of experience…
  • 3.5
    ON Semiconductor – Sunnyvale, CA
    $110k-$144k(Glassdoor est.)
    7 days ago 7d
    solutions. Products producedby the company help designengineers solve their unique design challenges inautomotive, communications, computing… digital designengineer at ONSemiconductor, you will lead and execute all aspects ofdigital development including RTL design, DFT,…
  • 3.8
    Marvell Technology – Santa Clara, CA
    25 days ago 25d
    tools, IP, and design flows PREFERRED QUALIFICATIONS: • Relevant experience with ASICphysicaldesign and timing closure… with 5 years DFT experience • Solid understanding of full ASICdesign flow • Ability to multi-task, set priorities, leads, and…
  • 3.6
    Broadcom – Sunnyvale, CA
    $109k-$140k(Glassdoor est.)
    24 days ago 24d
    verification, and of ASICdesign methodology Experience in one or more of the following areas is desired: mimo, ofdm, agc, channel… complex, highly integrated ASICs. Desired Skills and Qualifications: Typically a BS degree and 12 years of experience…
  • 3.7
    Keysight Technologies – Santa Clara, CA
    $108k-$149k(Glassdoor est.)
    11 days ago 11d
    member of a tight-knit group of highly skilled mixed-signal ASICengineers, your research leadership will push the boundaries of circuit… Experience with modern EDA tools used in IC design from design capture through physicaldesign and verification. • Familiarity with…
  • 4.4
    Embedded Resource Group – Mountain View, CA
    28 days ago 28d
    Description PhysicalDesignEngineer The individual will be responsible for back-end ASICDesign including physical place and… Experience in backend ASICdesign including place and route, static timing analysis, physical verification (LVS/DRC). Experience…
  • 4.4
    Google – Mountain View, CA
    $128k-$168k(Glassdoor est.)
    17 days ago 17d
    expert, you will design and optimize image processing algorithms and convert them into power efficient ASIC solutions using the… verification, physicaldesign, power optimization) Interest in consumer cameras and photography. Knowledge of hardware design paradigms…
  • 3.4
    Achronix Semiconductor – Santa Clara, CA
    $84k-$113k(Glassdoor est.)
    10 days ago 10d
    process technology. Position Profile Name: Hardware EngineerPhysicalDesign, Core Technology Requisition No.: 6200-1008… Experience running SPICE simulations Experience with commercial ASIC CAD tools (e.g., DC, ICC, PrimeTime) Experience with commercial…
  • 4.1
    Nokia – Sunnyvale, CA
    15 days ago 15d
    blocks Knowledge with digital ASICphysicaldesign flows. Knowledge of digital ASIC RTL design flow. Experience with mixed-… wireless communications! We are now looking for R&D manager, 5G ASIC integration to join our team. Key responsibilities In this…
  • 3.7
    Dialog Semiconductor – Campbell, CA
    $83k-$113k(Glassdoor est.)
    6 days ago 6d
    experience in ASICdesign. MSEE in digital design. RTL logic design in Verilog. Good understanding of ASICdesign flow. Self-motivated… verification. Collaboration with analog engineers and test engineers on analog testability design and debugging. Work closely with…
  • 3.5
    Cavium – San Jose, CA
    $99k-$134k(Glassdoor est.)
    30+ days ago 30d+
    with the physicaldesign teams in aiding the implementation of the functional blocks. Requirements: Engineering degree… Experience in Micro-architecture for the complex Custom/ASIC products focusing in any one/more areas: NPU, Embedded Processors, DSP, Graphics…
  • Cohere Technologies, Inc – Santa Clara, CA
    27 days ago 27d
    directly to the VP of Engineering. Required Qualifications: 5+ years of experience managing an ASICdesign team, with demonstrated… sized teams Must have experience in ASIC vendor management related to package design, SI analysis, silicon testing, characterization…
  • 3.4
    Micron Technology, Inc. – Milpitas, CA
    $115k-$152k(Glassdoor est.)
    10 days ago 10d
    of these products. You will collaborate with ASICdesigners and other engineering departments including system architecture, hardware… track record as the lead architect and RTL designer of Gen3 PCI Express IP / ASICs that is in production in multiple customers…
  • 3.3
    Omnivision Technologies, Inc – Santa Clara, CA
    17 days ago 17d
    equivalent and 5 years of ASICdesign experience Experience in all aspects of chip development: from design specification, defining… architecture, micro-architecture, RTL design and functional verification, Synthesis, PhysicalDesign, Timing closure, Tape-out, and post-Si…
  • 4.0
    Mentor Graphics – Fremont, CA
    $100k-$136k(Glassdoor est.)
    27 days ago 27d
    these phases in the physicaldesign flow for large digital ASIC or COT flow SoC (System-on-Chip) designs is required. Experience… exchanging ideas with other application engineers, helping users find solutions to their physicaldesign challenges, and debugging issues…
  • 3.5
    Advanced Micro Devices, Inc. – Sunnyvale, CA
    $92k-$124k(Glassdoor est.)
    30 days ago 30d+
    RESPONSIBILITY: Working on ASIC DFT/DFX IP design Developing IP automation flow Working on RTL design Working on block… development JOB COMPLEXITY: Proficient in RTL design Experience with ASIC front end integration flow Excellent written…
  • 3.7
    Dialog Semiconductor – Campbell, CA
    $97k-$131k(Glassdoor est.)
    14 days ago 14d
    8+ years of direct experience in ASIC/IC design with deep knowledge of whole IC design flow from RTL coding and verification… either Verilog or VHDL RTL coding and ASICdesign methodology. Competence in developing design constraints for synthesis, STA and…
  • Fujitsu Network Communications – Sunnyvale, CA
    14 days ago 14d
    Design for ASIC using Socionext Advanced Standard Cell technology. The Staff PhysicalDesignEngineer will have opportunities to work… Experience with 5 or more Chip Designs Experience in ASIC/COT design flow. Experience in PhysicalDesign Implementation which…
  • 3.5
    Zilog, Inc. – Milpitas, CA
    $66k-$93k(Glassdoor est.)
    NEW
    preferred with 6+ years of Digital DesignEngineering related experience. Skills in ASICdesign (gate, RTL, behavioral). Skills… timing analysis. Support physical verification. Perform silicon validation. Evaluate and improve design flows and methodologies…
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