268 jobs for ASIC Verification Engineer in San Jose, CA | Glassdoor
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ASIC Verification Engineer Jobs in San Jose, CA

268 Jobs

  • 4.4
    VeriSilicon Holdings Co., Ltd. – San Jose, CA
    EASY APPLY
    $90k-$119k(Glassdoor est.)
    7 days ago 7d
    skills in Verilog Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design… micro-architecture, implementation (using Verilog), and verification. Expected skills: 5+ years hands-on experience with…
  • 3.6
    Broadcom – San Jose, CA
    $101k-$136k(Glassdoor est.)
    7 days ago 7d
    a strong and expert level ASICVerificationEngineer in the area of PCIe SSD Controller verification working with the latest, greatest… / SoC verification using UVM, OVM or System Verilog. Expertise in developing block level / system level verification environments…
  • 3.9
    Cisco Systems – San Jose, CA
    $113k-$153k(Glassdoor est.)
    8 days ago 8d
    other engineers. Skills Required: Experience in high-performance ASICverification. Good understanding of ASIC design… micro-architecture specification and reviews. Engage in verification environment architecture and methodology development. Drive…
  • 3.6
    Systel – San Jose, CA
    19 days ago 19d
    Role & Responsibilities Will participate in ASIC design verification for high end switching products. Responsibilities include… Phyton scripts are essential. Must be familiar with ASIC design and verification methodologies and languages including Verilog, systemVerilog…
  • 4.4
    Google – Mountain View, CA
    $97k-$122k(Glassdoor est.)
    NEW
    interacting with design engineers to identify important verification scenarios. Create a constrained-random verification environment using… with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and…
  • 4.4
    NVIDIA – Santa Clara, CA
    $141k-$189k(Glassdoor est.)
    27 days ago 27d
    looking for a Senior ASICVerificationEngineer: NVIDIA is seeking an elite ASICVerificationEngineer to verify the design… position, you will be working on verifying ASIC design using advanced verification methodologies. You are expected to understand…
  • 3.2
    Rambus – Sunnyvale, CA
    $105k-$143k(Glassdoor est.)
    7 days ago 7d
    teams including ASIC design engineers and architects, other verificationengineers and system test engineers, security experts… Francisco or Sunnyvale office. This engineer will participate in the verification of secure ASIC cores developed by RSD, working with…
  • 4.4
    Embedded Resource Group – San Jose, CA
    28 days ago 28d
    Job Description ASICVerificationEngineerASICverification for SSD controller System-on-Chip. Participate in definition… Required Skills: 3-10 years experience in ASICverification UVM and SystemVerilog Additional Information…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    $114k-$155k(Glassdoor est.)
    5 days ago 5d
    Maintenance and support of the verification platform Requirements: 7+ years of SoC/ASICverification experience Hands on experience… Development of the verification IPs and integration in the verification platform Definition of the verification plan in collaboration…
  • 2.8
    cPacket Networks – San Jose, CA
    $83k-$115k(Glassdoor est.)
    8 days ago 8d
    This role will require candidates to develop and integrate the current and future RTL designs into a UVM environment.…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    $94k-$129k(Glassdoor est.)
    NEW
    Requirements: 3+ years of SoC/ASICverification experience Hands on experience using UVM SSD controller experience is preferred… definition and implementation of the verification platform, and the coordination of the verification activity. Responsibilities:…
  • 3.7
    Intel – San Jose, CA
    $95k-$130k(Glassdoor est.)
    28 days ago 28d
    Electrical Engineering or related field. 2+ years of experience on the following fields: Verification experience in FPGA, ASIC or custom… Job Description As a Design VerificationEngineer for high speed digital design you will work at Sub-system and Full Chip level…
  • 4.4
    NVIDIA – Santa Clara, CA
    $141k-$189k(Glassdoor est.)
    9 days ago 9d
    looking for a Senior ASICVerificationEngineer: NVIDIA is seeking elite ASICVerificationEngineers to verify the design and… responsible for verification of the ASIC design, architecture, golden models and micro-architecture using advanced verification methodologies…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    $95k-$129k(Glassdoor est.)
    NEW
    engineers to identify important verification scenarios. Create a constrained-random verification environment using SystemVerilog… with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and…
  • 3.2
    Aquantia – San Jose, CA
    EASY APPLY
    $83k-$104k(Glassdoor est.)
    26 days ago 26d
    understanding of digital design verification methodologies and tools including: • Expertise in creating verification infrastructure using… Responsibilities: • Responsible to define and implement verification architectures for mixed signal data communications semiconductors…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    $106k-$144k(Glassdoor est.)
    NEW
    the SSD Controller ASICverification methodology and environment development Detailed module verification testplan, covering… chip level verification Validate SoC design in FPGA prototyping and emulation platforms Work closely with FW engineers to resolve…
  • ASICSoft, Inc. – San Jose, CA
    17 days ago 17d
    Title: Digital VerificationEngineer (#: 1958336) Location: San Jose, CA Duration: 6 12 month contract As a key member… SOC infrastructure, chip bring-up and employ best-in-class verification methodology. You will have a great opportunity to work on…
  • 4.4
    Semi Conductor – San Jose, CA
    8 days ago 8d
    experience in ASIC Logic Functional Verification Preferred skills: Strong background in design verification, Knowledge of… Candidates must have experience performing ASICVerification based on architectural/micro-architectural specification review and…
  • 3.7
    Xilinx – San Jose, CA
    $108k-$137k(Glassdoor est.)
    6 days ago 6d
    Wireless FDST Verification group is looking for a Senior Design VerificationEngineer to contribution on FPGA block… DDR4, PCIe verification is a plus. Verification experience in performance verification is a plus Verification experience in…
  • 3.7
    Infinera – Sunnyvale, CA
    $119k-$161k(Glassdoor est.)
    NEW
    in ASICverification field. Should have worked on developing/implementing test plans at the chip-level for complex ASICs.… development and execution of self-checking tests for complex digital ASICs. Infinera is an equal opportunity employer. All qualified…
  • 3.9
    Ambarella – Santa Clara, CA
    $70k-$91k(Glassdoor est.)
    5 days ago 5d
    test plan, random and directed test cases, performing logic verification, and functional coverage analysis. * Developing frontend… SystemVerilog, Verilog and Perl. * Knowledge of design verification, and functional coverage. * Ability to program scripting…
  • 3.9
    Fortinet – Sunnyvale, CA
    $105k-$137k(Glassdoor est.)
    19 days ago 19d
    top-notch ASICengineer to join our front end design team. The team is responsible for designing Fortinet’s next generation ASICs accelerating… Experience in formal verification  Experience working with FPGA emulation  Experience in SOC verification  Hands on experience…
  • 3.1
    Toshiba – San Jose, CA
    $137k-$185k(Glassdoor est.)
    30+ days ago 30d+
    in managing & leading a HW verification team. Education MSEE or PhD in Electrical Engineering or Computer Science… deployment of the verification methodology Drive development of the verification IPs and integration in the verification platform…
  • 3.3
    Sony Electronics – San Jose, CA
    $91k-$124k(Glassdoor est.)
    22 days ago 22d
    develop and implement solutions Familiarity with ASIC/SoC design/verification methodologies Ability to write detailed and clear… leader in image sensors, is seeking a staff VLSI/ASIC logic Design Engineer to work on our next generation image sensor products…
  • 3.9
    Cisco Systems – San Jose, CA
    $106k-$148k(Glassdoor est.)
    8 days ago 8d
    Title: ASIC Physical Design Engineer Location: San Jose, CA WHO YOU'LL WORK WITH: Our creative and talented team as Physical… Physical Design lead in San Jose, CA. You will work with ASIC Front-end teams to understand chip architecture and drive physical…
  • 3.6
    Redolent, Inc. – Santa Clara, CA
    21 days ago 21d
    requirement with our direct client: Title: Specman Engineer (ASICVerification) Location: Santa Clara, CA Duration: 6+… At least 5+ Yr hands-on ASICverification experience; Wireless communication/DSP chip verification experience is must; Hands-on…
  • 3.5
    Cavium, Inc. – San Jose, CA
    $98k-$136k(Glassdoor est.)
    NEW
    such as UVM. Responsibilities: Contribute as an ASICVerificationEngineer developing the next generation of cloud, networking… directly with senior members of the ASIC team to develop comprehensive, state of the art, verification environment using the latest methodology…
  • 3.7
    Qualcomm – San Jose, CA
    $111k-$149k(Glassdoor est.)
    27 days ago 27d
    exposure, and get opportunity to lead SOC verification efforts and be part of the full ASIC life cycle from concept to tapeout to… Job Id E1947330 Job Title Digital VerificationEngineer Post Date 05/23/2017 Company - Division…
  • 3.8
    Marvell Technology – Santa Clara, CA
    23 days ago 23d
    motivated engineer to join our team. - BS/MS in EE, CE, CS, required. - A minimum 5 years of experience with digital ASIC design… developing corresponding verification plans. Designing and developing components of our verification environment using UVM, System…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    $111k-$152k(Glassdoor est.)
    8 days ago 8d
    technical oversight. Basic Qualifications FPGA & ASICVerification experience. Language Proficient in VHDL/Verilog for… ASIC & FPGA development on R&D program. Senior engineer with experience in developing, testing, and integrating digital signal…
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