Senior ASIC Design Engineer Jobs in San Jose, CA | Glassdoor
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Senior ASIC Design Engineer Jobs in San Jose, CA

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  • 4.4
    VeriSilicon Holdings Co., Ltd. – San Jose, CA
    EASY APPLY
    Est. Salary $89k-$119k
    6 days ago 6d
    -end complex RTL design Programming skills in Verilog Must be familiar with all stages of the ASICdesign flow (including specification… of computer graphics and low-power design techniques a plus Experience of GPU shader design a plus…
  • 3.8
    Encore Semi – San Jose, CA
    EASY APPLY
    Est. Salary $105k-$143k
    NEW
    Successful ASIC Digital DesignEngineer will be responsible for participating in, the design of leading edge ASICs for multi-function… ASIC Digital DesignEngineer Work Location: San Jose, CA Status: Permanent - Full-time Compensation: Salary + Bonus +…
  • 3.6
    Xilinx – San Jose, CA
    Est. Salary $93k-$126k
    14 days ago 14d
    definition, design, verification, and documentation for Xilinx ASIC development. Determine architecture design, logic design, and system… Electrical Engineering, Computer Engineering or related field plus 5 years of progressive experience as DesignEngineer, System Design…
  • 2.8
    cPacket Networks – San Jose, CA
    Est. Salary $80k-$108k
    6 days ago 6d
    expected to be able to design, implement and test both unit level modules and higher level architecture designs. Candidates should… should be comfortable understanding tradeoffs in the design and be able to articulate them. This role requires being able to develop…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $122k-$165k
    NEW
    As a senior member of the SOC Design team you will be responsible for the following 1) Microarchitecture and design of RTL… system Design, Design verification, Physical Design, DFT, and power teams to achieve first tapeout success on designs 4)…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $122k-$165k
    14 days ago 14d
    analysis team. Develop/debug RTL design of different sections of the cache. Work with physical design team to close timing of the…
  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $112k-$152k
    6 days ago 6d
    Experience in high-performance ASIC verification. Good understanding of ASICdesign and verification methodologies and flows… collaboration with design, software and hardware teams to ensure a successful product delivery. Mentor and enable other engineers.…
  • Cohere Technologies, Inc – Santa Clara, CA
    Est. Salary $92k-$119k
    NEW
    open position for a Senior FPGA/ASICDesignEngineer in our Santa Clara office. In this position, you will design, implement and test… perform the detailed design and verification. This position reports directly to the Director of FPGA/ASICEngineering Required Qualifications…
  • 3.9
    Axelon, Inc. – San Jose, CA
    Est. Salary $98k-$134k
    5 days ago 5d
    We are currently looking for a SeniorASIC/SoC Verification Engineer (Contract Position) to join our team in San Jose, CA. He… Verification architecture and design of leading edge networking, storage, embedded computing ASIC and/ or FPGA. Responsibilities…
  • Approgence – San Jose, CA
    Est. Salary $79k-$107k
    12 days ago 12d
    Job Title : SeniorASIC/ RTL DesignEngineer with DSP Job Location : San Diego & San Jose, CA Job Description : This… perform bit-exact simulation. - Modem ASICDesign team is working with physical designengineer to deliver netlist, spec timing constraints…
  • 2.7
    SK Hynix Memory Solutions – San Jose, CA
    Est. Salary $92k-$118k
    21 days ago 21d
    Descriptions: The ASICDesignEngineer will be working on the leading edge SSD controller IP design from architecture to production… support physical design and system level analysis. Qualifications: BS, MS, or PhD in Electrical Engineering with 5-10 years…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    Est. Salary $83k-$111k
    26 days ago 26d
    Digital Processor ASIC/FPGA Designer: The SeniorASIC/FPGA DesignEngineer will be working in the RF Center of Excellence (… (RF CoE). The Senior FPGA/ASICdesigner will provide technical support to the RF COE ASIC/FPGA design Team. The individual…
  • 3.8
    Marvell Technology – Santa Clara, CA
    Est. Salary $101k-$127k
    12 days ago 12d
    timing simulation and verification, preparing design review. Work with testing engineer to evaluate, validate and debug silicon device… Responsible for design, development, modification and evaluation of high-speed digital circuit for signal processing components…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $140k-$188k
    NEW
    for a SeniorASIC Verification Engineer: NVIDIA is seeking an elite ASIC Verification Engineer to verify the design and implementation… working on verifying ASICdesign using advanced verification methodologies. You are expected to understand the design and verify correctness…
  • 2.9
    Toshiba America Electronic Components – San Jose, CA
    EASY APPLY
    Est. Salary $93k-$127k
    25 days ago 25d
    , and building random/directed test benches. Working with design team and firmware team. Provides technical guidance to other…
  • 3.2
    Rambus – Sunnyvale, CA
    Est. Salary $102k-$139k
    5 days ago 5d
    teams including ASICdesignengineers and architects, other verification engineers and system test engineers, security experts… Rambus Security Division (RSD) is hiring a talented SeniorASIC Verification Engineer to join our world class technology team in our…
  • 3.2
    Avago Technologies – Santa Clara, CA
    Est. Salary $103k-$135k
    20 days ago 20d
    work with designengineers to verify fixes. ○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. ○… Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: ○ Architect block…
  • 3.6
    Broadcom – Santa Clara, CA
    Est. Salary $102k-$137k
    20 days ago 20d
    work with designengineers to verify fixes. ○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. ○… Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: ○ Architect block…
  • 3.8
    Marvell Technology – Santa Clara, CA
    Est. Salary $93k-$118k
    21 days ago 21d
    closure. * MS in EE with 3 years of work experience in SOC/ASIC/IP development. * Must have knowledge and experience of HDL… Knowledge of UVM and System Verilog is required. * Background in ASIC implementation including lint, CDC, synthesis, formal and static…
  • 3.1
    Toshiba – San Jose, CA
    Est. Salary $69k-$95k
    30+ days ago 30d+
    , and building random/directed test benches. Working with design team and firmware team. Provides technical guidance to other…
  • 4.0
    Inphi Corporation – Santa Clara, CA
    Est. Salary $138k-$177k
    14 days ago 14d
    exciting career opportunity. The Candidate Title: Senior Software Designer Location: Kanata, Ontario Description: As… following areas: Low level software development in C Multi-ASIC system software validation High level GUI development in Qt…
  • Advanced Technology Search – San Jose, CA
    Est. Salary $92k-$143k
    NEW
    Job Description ASIC/IP Verification EngineerASIC/Layout DesignEngineer: Oversees definition, design, verification, and… development, part of the ASIC solution for storage applications. They are looking for a Senior Verification Engineer, who will be a key…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    Est. Salary $127k-$167k
    26 days ago 26d
    Digital Processor ASIC/FPGA Designer: The Senior Staff ASIC/FPGA DesignEngineer will be working in the RF Center of Excellence… the effort to meet the customer requirements. The Senior Staff FPGA/ASICdesigner will provide technical support across the enterprise…
  • 3.4
    Tektronix – Santa Clara, CA
    Est. Salary $102k-$135k
    9 days ago 9d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $100k-$127k
    6 days ago 6d
    * Experience in high-performance ASIC verification. * Good understanding of ASICdesign and verification methodologies and… verification of complex, high-performance, and highly integrated ASICs used in Cisco's networking products. Responsibilities: *…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    Est. Salary $112k-$153k
    7 days ago 7d
    ASIC & FPGA development on R&D program. Seniorengineer with experience in developing, testing, and integrating digital signal… Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $140k-$188k
    7 days ago 7d
    looking for a SeniorASIC Verification Engineer: NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation… be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading…
  • 3.7
    Fortive – Santa Clara, CA
    Est. Salary $95k-$126k
    9 days ago 9d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • 3.7
    Intel – San Jose, CA
    Est. Salary $93k-$117k
    NEW
    As a SeniorDesign Verification Engineer for high speed digital design you will work closely with an energetic design engineering… with 10+ years of verification experience in FPGA, ASIC or custom IC designs o Experience with high-speed transceiver protocols…
  • 3.6
    Xilinx – San Jose, CA
    Est. Salary $93k-$126k
    27 days ago 27d
    tasks include definition, design, verification, and documentation for Xilinx testchips development (ASIC Internal only). Determine… on CMOS circuit design, verification, Silicon testing and characterization of digital and analog testchips (ASIC Internal only).…
  • 3.7
    Intel – Santa Clara, CA
    Est. Salary $87k-$121k
    16 days ago 16d
    NGS) 5G BBIC team, we are looking for a senior level Front End Design Automation Engineer to join the 5G Mobile Wireless Technology… Frontend Design Automation Engineer, you will be responsible for driving methodology, and productivity improvements in design flows…
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