Senior ASIC Verification Engineer Jobs in San Jose, CA | Glassdoor
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Senior ASIC Verification Engineer Jobs in San Jose, CA

74 Jobs

  • 4.4
    VeriSilicon Holdings Co., Ltd. – San Jose, CA
    EASY APPLY
    $90k-$119k(Glassdoor est.)
    8 days ago 8d
    skills in Verilog Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design… micro-architecture, implementation (using Verilog), and verification. Expected skills: 5+ years hands-on experience with…
  • 3.9
    Cisco Systems – San Jose, CA
    $113k-$153k(Glassdoor est.)
    8 days ago 8d
    other engineers. Skills Required: Experience in high-performance ASICverification. Good understanding of ASIC design… micro-architecture specification and reviews. Engage in verification environment architecture and methodology development. Drive…
  • 3.2
    Rambus – Sunnyvale, CA
    $105k-$143k(Glassdoor est.)
    7 days ago 7d
    Rambus Security Division (RSD) is hiring a talented SeniorASICVerificationEngineer to join our world class technology team in our… teams including ASIC design engineers and architects, other verificationengineers and system test engineers, security experts…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    $95k-$129k(Glassdoor est.)
    NEW
    engineers to identify important verification scenarios. Create a constrained-random verification environment using SystemVerilog… with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and…
  • 4.4
    NVIDIA – Santa Clara, CA
    $141k-$189k(Glassdoor est.)
    27 days ago 27d
    now looking for a SeniorASICVerificationEngineer: NVIDIA is seeking an elite ASICVerificationEngineer to verify the design… position, you will be working on verifying ASIC design using advanced verification methodologies. You are expected to understand…
  • 3.7
    Xilinx – San Jose, CA
    $108k-$137k(Glassdoor est.)
    6 days ago 6d
    Wireless FDST Verification group is looking for a Senior Design VerificationEngineer to contribution on FPGA block… DDR4, PCIe verification is a plus. Verification experience in performance verification is a plus Verification experience in…
  • 3.6
    Samsung Semiconductor, Inc. – San Jose, CA
    12 days ago 12d
    roadmaps. We are currently looking for a SeniorASIC/SoC Verification/Design Engineer to join our team in San Jose, CA. He or she… storage, and compute ASIC/ FPGA and system solutions. The candidate will primarily focus on the RTL verification activities and will…
  • 4.4
    NVIDIA – Santa Clara, CA
    $141k-$189k(Glassdoor est.)
    9 days ago 9d
    now looking for a SeniorASICVerificationEngineer: NVIDIA is seeking elite ASICVerificationEngineers to verify the design… responsible for verification of the ASIC design, architecture, golden models and micro-architecture using advanced verification methodologies…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    $93k-$120k(Glassdoor est.)
    NEW
    synthesis and gate-level simulation tasks Assisting in verification and timing of the entire chip…
  • 3.8
    Marvell Technology – Santa Clara, CA
    $94k-$119k(Glassdoor est.)
    23 days ago 23d
    closure. * MS in EE with 3 years of work experience in SOC/ASIC/IP development. * Must have knowledge and experience of HDL… Knowledge of UVM and System Verilog is required. * Background in ASIC implementation including lint, CDC, synthesis, formal and static…
  • 3.9
    Cisco Systems – San Jose, CA
    $101k-$129k(Glassdoor est.)
    8 days ago 8d
    Experience in high-performance ASICverification. Good understanding of ASIC design and verification methodologies and flows.… Participate in the architecture and verification of complex, high-performance, and highly integrated ASICs used in Cisco's networking products…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    $111k-$152k(Glassdoor est.)
    8 days ago 8d
    ASIC & FPGA development on R&D program. Seniorengineer with experience in developing, testing, and integrating digital signal… technical oversight. Basic Qualifications FPGA & ASICVerification experience. Language Proficient in VHDL/Verilog for…
  • 4.4
    NVIDIA – Santa Clara, CA
    NEW
    We are now looking for a SeniorASIC Power Engineer: NVIDIA is seeking extraordinary power engineers to design hardware accelerators… designers, verification and VLSI teams to accomplish your tasks​ What we need to see: BS or MS in electrical engineering or computer…
  • 3.5
    Cavium, Inc. – San Jose, CA
    $98k-$136k(Glassdoor est.)
    NEW
    work directly with senior members of the ASIC team to develop comprehensive, state of the art, verification environment using the… such as UVM. Responsibilities: Contribute as an ASICVerificationEngineer developing the next generation of cloud, networking…
  • Cohere Technologies, Inc – Santa Clara, CA
    $95k-$124k(Glassdoor est.)
    4 days ago 4d
    detailed design and verification. This position reports directly to the Director of FPGA/ASICEngineering Required Qualifications… the team? We have an open position for a Senior FPGA/ASIC Design Engineer in our Santa Clara office. In this position, you…
  • 3.7
    Intel – San Jose, CA
    $93k-$118k(Glassdoor est.)
    4 days ago 4d
    Job Description As a Senior Design VerificationEngineer for high speed digital design you will work closely with an energetic… following: o BSEE or MSEE with 10+ years of verification experience in FPGA, ASIC or custom IC designs o Experience with high-…
  • Approgence – San Jose, CA
    $83k-$112k(Glassdoor est.)
    13 days ago 13d
    analysis and post silicon verification support. Modem ASIC Design team is working with system engineer to understand wireless standards… Job Title : SeniorASIC/ RTL Design Engineer with DSP Job Location : San Diego & San Jose, CA Job Description : This…
  • 3.4
    Micron Technology, Inc. – Milpitas, CA
    $114k-$158k(Glassdoor est.)
    4 days ago 4d
    architect, and developer of a UVM verification environment for verification of a controller ASIC and associated system performance… Req. ID: 87278 As a Senior Staff VerificationEngineer in the System Modeling Group at Micron Semiconductor Products, Inc…
  • 4.4
    NVIDIA – Santa Clara, CA
    $141k-$189k(Glassdoor est.)
    NEW
    today. We are now looking for a Senior DFT VerificationEngineer. Design-for-Test Engineering at NVIDIA works on groundbreaking… coverage driven verification closure. You will collaborate closely with cross-functional teams like chip architecture, ASIC design, functional…
  • 3.7
    Xilinx – San Jose, CA
    $128k-$170k(Glassdoor est.)
    19 days ago 19d
    optimizations, logic optimization and technology mapping algorithms for ASIC or FPGA synthesis tools is desirable. Hands on experience in… and exposure to using Verilog/VHDL simulators and formal verification tools.…
  • 3.1
    Toshiba America Electronic Components – San Jose, CA
    $94k-$129k(Glassdoor est.)
    NEW
    Requirements: 3+ years of SoC/ASICverification experience Hands on experience using UVM SSD controller experience is preferred… definition and implementation of the verification platform, and the coordination of the verification activity. Responsibilities:…
  • 4.1
    Nokia – Sunnyvale, CA
    13 days ago 13d
    techniques. As a SeniorEngineer, 5G ASIC Design, you will effectively communicate your design ideas to fellow engineers and R&D Manager… wireless communications! We are now looking for SeniorEngineer, 5G ASIC Design to join our team. Key responsibilities…
  • 3.5
    Cavium, Inc. – San Jose, CA
    $83k-$108k(Glassdoor est.)
    NEW
    processors. You will work directly with senior members of the ASIC team to learn and design state of art high speed digital systems. Responsibilities… static timing closure, formal verification, gate-level simulations, and block-level function verification. Preferred/Plus: Experience…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    $103k-$141k(Glassdoor est.)
    8 days ago 8d
    synthesis, and perform timing analysis Work with Design Verification and emulation team to validate design Develop functional… would be a plus but not required Experience with Universal Verification Methodology (UVM) is a plus, but not required Experience…
  • 3.6
    Broadcom – Santa Clara, CA
    $103k-$139k(Glassdoor est.)
    22 days ago 22d
    with design engineers to verify fixes. ○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. ○ Replicate… initiatives. As a verificationengineer, your responsibilities will include: ○ Architect block and full-chip verification environments…
  • 3.1
    Huawei Technologies – Santa Clara, CA
    20 days ago 20d
    We are seeking an ASIC Design Engineer to be an important team member in the research, design and verification of SoCs for next… innovation to deliver a better future...faster. Senior Staff Engineer - ASIC Design Location: Santa Clara, CA (R&D) Req…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    $93k-$120k(Glassdoor est.)
    23 days ago 23d
    Descriptions: The ASIC Design Engineer will be working on the leading edge SSD controller IP design from architecture to… Drive architecture or storage systems, DDR, PCIe, UVM based verification.…
  • 2.7
    Microsemi – San Jose, CA
    $103k-$139k(Glassdoor est.)
    14 days ago 14d
    -10% Job Category: Engineering Job Description: The Verification team is responsible for verification of the custom FPGA centric… radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices…
  • 3.4
    Tektronix – Santa Clara, CA
    $89k-$117k(Glassdoor est.)
    NEW
    Job Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers… Requirements o Internship/industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity…
  • 3.8
    Fortive – Santa Clara, CA
    $83k-$110k(Glassdoor est.)
    NEW
    Job Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers… Requirements o Internship/industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity…
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