Soc Physical Design Engineer Jobs in San Jose, CA | Glassdoor

Soc Physical Design Engineer Jobs in San Jose, CA

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  • 2.5
    SK Hynix Memory Solutions – San Jose, CA
    Est. Salary $88k-$113k
    2 days ago 2d
    PhD degree in Electrical Engineer with 7-10 years of direct experience in SOC/ASIC design Expertise in Verilog, synthesis, debug… Verification and emulation team to validate design Work with Physical Design team to implement design Requirements: BS, MS, or PhD…
  • 3.4
    Rambus – Sunnyvale, CA
    Est. Salary $151k-$189k
    23 days ago 23d
    collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation… silicon-based technologies such as IO, processor, and memory and SOC-based IPs You will work in a dynamic and interdisciplinary R…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $116k-$162k
    3 days ago 3d
    responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing state… Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ . Description Work with logic design team to understand…
  • 3.7
    Intel – Santa Clara, CA
    Today 9hr
    management of SoC design execution including RTL design & verification 8+ years emulation/Co-validation and Physical Design leading… other SoC components in a baseband modem. Responsible for architecture and SoC design execution spanning RTL design, integration…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $101k-$138k
    3 days ago 3d
    member of SoC Power team, you will be involved in various stages and aspects of the power optimization efforts of mobile SOC CPU block… issues. This role requires close collaboration with RTL, Physical design, Verification, Circuit and CAD teams, hence strong communication…
  • 3.7
    Synapse Design – Santa Clara, CA
    Est. Salary $90k-$124k
    3 days ago 3d
    : BS, MS in electrical engineering or computer engineering Experience using Synopsys ICC or Cadence SOC Encounter Successful tapeout… experience Job Description : Responsible for place/route of complex SoCs in advanced process technologies Define the floorplan, including…
  • 3.7
    Intel – Santa Clara, CA
    Est. Salary $79k-$121k
    15 days ago 15d
    aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that… this position, you will be working alongside a World-class SOC design team within the Scalable Performance CPU Development Group…
  • 4.0
    Intrinsix – San Jose, CA
    3 days ago 3d
    experience in ASIC/SoC design and development Applicant must have a Master’s Degree or PhD in Electrical Engineering, Computer Engineering… and growing a team of engineers. Qualifications: 15+ years of experience in High Performance ASIC & SoC development High…
  • 3.4
    Rambus – Sunnyvale, CA
    8 days ago 8d
    collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation… Performance. BS/MS in computer science, computer engineering, software engineering, or related degree preferred; but substantial,…
  • 3.6
    Qualcomm – San Jose, CA
    Est. Salary $109k-$149k
    10 days ago 10d
    Job Id E1951504 Job Title Physical Design Engineer - Timing Closure Post Date 01/17/2017 Company -… Job Area Engineering - Hardware Location California - San Jose Job Overview Qualcomms Physical Design team implements…
  • 3.7
    Intel – Santa Clara, CA
    2 days ago 2d
    Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products… In-depth technical knowledge of contemporary SoC engineering practice and design flows, plus current process node structures and…
  • 4.0
    Apple – Santa Clara, CA
    15 days ago 15d
    with the hardware design engineers. •Exploring thermal/power requirements with the power team and physical design team. •C/C++ modeling… analyze the trade-offs of design alternatives. •Integration with SOC models from the architecture and design teams. •Running simulations…
  • 3.3
    Cavium, Inc. – San Jose, CA
    Est. Salary $129k-$179k
    3 days ago 3d
    industry standard EDA tools for designing the next generation Multi-Ghz high-performance processor SOC chips in leading-edge CMOS process… sure all the blocks meet physical requirements. Implement/Support blocks with multi-voltage designs through all aspects of RTL…
  • 3.6
    Qualcomm – San Jose, CA
    Est. Salary $109k-$149k
    16 days ago 16d
    Job Id E1952490 Job Title Physical Design Engineer - Static Timing Analysis (STA) - Server SoC Post Date 02/08/2017… responsible for closing timing on block/top level designs, working we PD engineers and SoC timing teams. Minimum Qualifications - Full-chip…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $117k-$152k
    3 days ago 3d
    responsible for physical verification of an SOC. Key Qualifications The ideal candidate will have 5-10 years of physical design experience… Physical Design Verification Engineer Job Number: 32821198 Santa Clara Valley, California, United States Posted: Mar. 28…
  • Yang Technical Solutions – San Jose, CA
    EASY APPLY
    15 days ago 15d
    Principal Physical Design/Timing Engineer Job Responsibilities Advanced process technology node engagement Design… EDI, StarRC-XT, Calibre, AOCV, timing closure Job Code: Physical Design Email: resumes@yangtechnical.catsone.com Phone: +1 919…
  • 3.7
    Intel – San Jose, CA
    17 days ago 17d
    requirement. - 2+ years of leading a small team of engineer to accomplish SoC Design Additional Preferred Qualifications: - Experience… success. As a SoC Design Lead you will oversee definition, design, verification, and documentation for SoC System on a Chip…
  • 2.9
    Avago Technologies – Santa Clara, CA
    2 days ago 2d
    Working in SOC with frequencies more that 1GHz is an advantage. Work effectively with design verification engineers to recommend… on at least two or more SoC design with direct participation in micro-architecture and logic design through tapeout. Knowledge of…
  • 3.0
    Cypress Semiconductor Corp. – San Jose, CA
    Est. Salary $80k-$113k
    Today 11hr
    verifying SoCs in which this IP (as well as others) is integrated. We are looking for a self-motivated and experienced engineer who… plan according to design Skills 1. Be proficient in Verilog/VHDL, be familiar with C/C++ 2. ARM based SOC verification experience…
  • 3.2
    Samsung Semiconductor, Inc. – San Jose, CA
    Est. Salary $80k-$109k
    22 days ago 22d
    bit-exact simulation. • Modem ASIC Design team is working with physical design engineer to deliver netlist, spec timing constraints… JOB TITLE Modem Staff/Senior ASIC/RTL Design Engineer Requisition ID DSA30701 OVERVIEW Fueled by the…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $119k-$162k
    7 days ago 7d
    members of the SoC Design, SoC Design Verification, System Verification, Firmware, Emulation, STA, and Physical Design teams to deliver… . ASIC Design Engineer, you will have responsibilities spanning all aspects of SoC design: •Working with other engineers that are…
  • 3.0
    Cypress Semiconductor Corp. – San Jose, CA
    Today 11hr
    minimum of 10+ years of relevant experience in IP/SoC design. Must have the following: - Proven expertise in Silicon product development… Job Segment: Electronics Engineer, Engineer, Electrical, Product Development, Design Engineer, Engineering, Research Posted by StartWire…
  • 3.7
    Intel – San Jose, CA
    Est. Salary $110k-$151k
    23 days ago 23d
    verify all levels of physical design hierarchy (leaf cell, IP block, compiler)- Collaborate closely with SoC projects at various… digital physical design assignments. - Work closely with circuit design engineers to interpret schematics and drive physical implementation…
  • 3.8
    Cavium – San Jose, CA
    Est. Salary $127k-$173k
    14 days ago 14d
    industry standard EDA tools for designing the next generation Multi-Ghz high-performance processor SOC chips in leading-edge CMOS process… Preferred/Plus: * Experience in tape-outs of high performance SOC is highly desired. * Understanding of several timing-related…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $104k-$147k
    7 days ago 7d
    with designers on STA, physical, power and logical issues Working with other engineers that are members of the SOC Design, SOC… SOC Design Verification, Emulation, STA, and Physical Design teams to deliver a high quality IP ‘s for the SOC
  • 2.7
    GLOBALFOUNDRIES – Santa Clara, CA
    Est. Salary $92k-$149k
    14 days ago 14d
    in Electrical Engineering Experience in SOC level (rather than block level) architecture of ARM-based SOCs Knowledgeable… our world-class SOC logic design and verification team! The ideal candidate will have experience integrating SOCs and be comfortable…
  • 2.7
    InvenSense – San Jose, CA
    Est. Salary $104k-$140k
    14 days ago 14d
    provider of SoC platform solutions, we definitely want to hear from you. Job Summary: Senior MEMS Design Engineer will be responsible… equivalent Strong engineering background in design and FEA simulation of MEMS devices. Experience designing MEMS acoustic and…
  • 3.7
    Intel – Santa Clara, CA
    Est. Salary $101k-$137k
    Today 10hr
    Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products… performance requirements, physical/structural design constraints (timing, area, power), as well as proprietary design rules and other quality…
  • 3.8
    Cavium – San Jose, CA
    Est. Salary $122k-$161k
    14 days ago 14d
    10+ years of experience in RTL design of submicron SOC products (eg: Microprocessor based SOC's). * Experience in Micro-architecture… is a plus. * Experience in designing high speed (>1 GHz)/high-performance embedded processor SOC products is a plus. * Knowledge…
  • 3.5
    Broadcom – Santa Clara, CA
    2 days ago 2d
    Working in SOC with frequencies more that 1GHz is an advantage. Work effectively with design verification engineers to recommend… on at least two or more SoC design with direct participation in micro-architecture and logic design through tapeout. Knowledge of…
Job Title Location Employer Salary
SOC/ASIC Design Engineer San Jose, CA SK Hynix Memory Solutions $88k-$113k
Principal Circuit Design Engineering Sunnyvale, CA Rambus $151k-$189k
Physical Design Engineer-PnR Santa Clara, CA Apple $116k-$162k
SoC Architecture and Design Lead Santa Clara, CA Intel $88k-$112k
SOC Power CAD engineer Santa Clara, CA Apple $101k-$138k
Senior Physical Design Engineer Santa Clara, CA Synapse Design $90k-$124k
Structural Design / RLS Engineer Santa Clara, CA Intel $79k-$121k
ASIC & SoC Technical Lead San Jose, CA Intrinsix $93k-$126k
SMTS II,SQA Engineering Sunnyvale, CA Rambus $138k-$176k
Physical Design Engineer - Timing Closure San Jose, CA Qualcomm $109k-$149k
SoC Functional Manager Santa Clara, CA Intel $111k-$169k
Platform Architect, SoC - Cache Santa Clara, CA Apple $108k-$138k
Lead Physical Design Engineer (Full Chip) - PDMK05 San Jose, CA Cavium, Inc. $129k-$179k
Physical Design Engineer - Static Timing Analysis (STA) - Server SoC San Jose, CA Qualcomm $109k-$149k
Physical Design Verification Engineer Santa Clara, CA Apple $117k-$152k
Principal Physical Design Engineer San Jose, CA Yang Technical Solutions $124k-$192k
SoC Design Lead San Jose, CA Intel $87k-$112k
R&D Engineer IC Design Santa Clara, CA Avago Technologies $101k-$133k
RFIC Design Engineer San Jose, CA Cypress Semiconductor Corp. $80k-$113k
ASIC/RTL Design Engineer San Jose, CA Samsung Semiconductor, Inc. $80k-$109k
ASIC Design Engineer Santa Clara, CA Apple $119k-$162k
Senior Physical Design Engineer San Jose, CA Intel $110k-$151k
Lead Physical Design Engineer (Full Chip) - PDMK05 San Jose, CA Cavium $127k-$173k
ASIC Design Integration Engineer Santa Clara, CA Apple $104k-$147k
SOC Architect and Front End Project Manager Santa Clara, CA GLOBALFOUNDRIES $92k-$149k
MEMS Design Engineer - Sr San Jose, CA InvenSense $104k-$140k
Senior Graphics Hardware Design Engineer Santa Clara, CA Intel $101k-$137k
Principal RTL Design Engineer-DEAS07 San Jose, CA Cavium $122k-$161k
R&D Engineer IC Design Santa Clara, CA Broadcom $106k-$136k
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