Job Type
Date Posted
Salary Range
Distance

Soc Physical Design Engineer Jobs in San Jose, CA

150Jobs

  • 3.4
    Sony Electronics – San Jose, CA
    $95k-$130k(Glassdoor est.)
    NEW
    then develop and implement solutions Familiarity with ASIC/SoCdesign/verification methodologies Ability to write detailed… complex digital designs but the Designengineer will also work closely with analog/algorithm/system engineers performing in depth…
  • 3.6
    Redolent, Inc – San Jose, CA
    EASY APPLY
    $61k-$86k(Glassdoor est.)
    6 days ago 6d
    fill position with our client Job Title: RTL DesignEngineers (SoCDesign) Location: San Jose, CA Duration:6+ Months… implementations, MATLAB, modeling) Physical Layer Design (USB, HDMI, DDR, MIPI) Digital Design for Mixed Signal ASICs (PLL, Phase-Lock-Loop…
  • 3.4
    Sony Electronics – San Jose, CA
    $86k-$132k(Glassdoor est.)
    HOT
    The Image Sensor Design Center (ISDC) in Sony Electronics currently has an opening for a Software Engineer in their San Jose… operating systems, device drivers, and board support packages SoC/FPGA/Embedded programming Must be able to work in a team environment…
  • 4.7
    Macropace Technologies – San Jose, CA
    EASY APPLY
    $82k-$114k(Glassdoor est.)
    13 days ago 13d
    and Physical Verification closure of SoC/sub-chips. Desired Skills and Experience: Experience in PhysicalDesign Handled… PHYSICALDESIGNENGINEER San Jose, CA Fulltime/ Contract Job Description: You will be part of a PhysicalDesign team…
  • 4.7
    Macropace Technologies – San Jose, CA
    EASY APPLY
    $82k-$106k(Glassdoor est.)
    14 days ago 14d
    and Physical Verification closure of SoC/sub-chips. Desired Skills and Experience: Experience in PhysicalDesign Handled… PHYSICALDESIGN ( VERIFICATION ENGINEER) San Jose, CA Fulltime/ Contract Job Description: You will be part of a Physical…
  • 4.0
    Apple – Santa Clara, CA
    $149k-$204k(Glassdoor est.)
    HOT
    of PhysicalDesign experience on high PHY and/or SOCdesigns Knowledge about industry standards and practices in Physical Design… As a PhysicalDesignengineer you will be involved with all phases of physicaldesign of high performance PHY design from RTL…
  • 3.7
    Intel – San Jose, CA
    $92k-$128k(Glassdoor est.)
    20 days ago 20d
    Architecture, Design Verification, PhysicalDesign, DFT, and power teams to achieve first tapeout success on designs Work with cross-functional… refinement of RTL design to target power, performance, area and timing goals. Working with physicaldesigners on timing constraints…
  • 4.5
    Xperi – San Jose, CA
    19 days ago 19d
    device physics particularly in DRAM and FD-SOI Physicaldesign experience SoC floorplanning knowledge Ability to travel domestically… Electrical Engineering, Device Physics, or other comparable field of study 10+ years of experience in device or SoC architecture…
  • 2.7
    L&T Technology Services – Milpitas, CA
    $88k-$116k(Glassdoor est.)
    NEW
    complex SOC's Experience in running STA analysis and achieving timing closure on multiple high-performance, low power designs Experience… complex SOC's Experience in running STA analysis and achieving timing closure on multiple high-performance, low power designs Experience…
  • 4.0
    Apple – Santa Clara, CA
    $106k-$144k(Glassdoor est.)
    8 days ago 8d
    SoCDesignEngineer Job Number: 113244049 Santa Clara Valley, California, United States Posted: Nov. 13, 2017 Weekly Hours… record of RTL design and timing closure on large complex designs •Expertise in: •SOC IP integration and RTL Design for performance…
  • 4.7
    Macropace Technologies – Santa Clara, CA
    EASY APPLY
    $61k-$88k(Glassdoor est.)
    NEW
    least two and preferably several): Chip design background in circuit/physicaldesign (timing closure, power, etc.) or DV (correlating… Comfortable working primarily in a lab environment with designers, software engineers. Strong scripting skills in one of the major…
  • 4.7
    Macropace Technologies – Santa Clara, CA
    EASY APPLY
    NEW
    least two and preferably several): Chip design background in circuit/physicaldesign (timing closure, power, etc.) or DV (correlating… Comfortable working primarily in a lab environment with designers, software engineers. Strong scripting skills in one of the major…
  • 3.6
    ON Semiconductor – San Jose, CA
    $78k-$112k(Glassdoor est.)
    Today 5hr
    connectivity, discrete, SoC and custom devices. The company's products help engineers solve their unique design challenges in automotive… ON-Semiconductor, you will work cross functionally with Product and DesignEngineers, to analyze failures in CMOS image sensors. Our image sensors…
  • 4.7
    Macropace Technologies – Santa Clara, CA
    EASY APPLY
    $61k-$88k(Glassdoor est.)
    NEW
    least two and preferably several): Chip design background in circuit/physicaldesign (timing closure, power, etc.) or DV (correlating… Comfortable working primarily in a lab environment with designers, software engineers. Strong scripting skills in one of the major…
  • 4.0
    Apple – Santa Clara, CA
    $122k-$154k(Glassdoor est.)
    7 days ago 7d
    for physical verification of an SOC. Key Qualifications The ideal candidate will have 5-10 years of physicaldesign experience… PhysicalDesign Verification Engineer Job Number: 32821198 Santa Clara Valley, California, United States Posted: Sep. 1…
  • 4.0
    Apple – Santa Clara, CA
    $112k-$156k(Glassdoor est.)
    NEW
    record of RTL design and timing closure on large complex designs Expertise in: SOC IP integration and RTL Design for performance… aspects of development design for large SOC blocks including: Internal and external IP integration, design of system bus and control…
  • 3.5
    Cavium, Inc. – San Jose, CA
    $117k-$174k(Glassdoor est.)
    5 days ago 5d
    100Gbps, Including MAC, PCS and Physical Layer PCB / Board design and bring-up practices Circuit design and schematic capture / layout… customers, partners, engineering, and sales counterparts in winning and supporting highly complex designs utilizing Cavium's product…
  • 3.5
    Cavium, Inc. – San Jose, CA
    $152k-$207k(Glassdoor est.)
    21 days ago 21d
    industry standard EDA tools for designing the next generation Multi-Ghz high-performance processor SOC chips in leading-edge CMOS process… sure all the blocks meet physical requirements. Implement/Support blocks with multi-voltage designs through all aspects of RTL…
  • 4.0
    Apple – Santa Clara, CA
    NEW
    with the hardware designengineers. Exploring thermal/power requirements with the power team and physicaldesign team. C/C++ modeling… analyze the trade-offs of design alternatives. Integration with SOC models from the architecture and design teams. Running simulations…
  • 3.6
    ON Semiconductor – San Jose, CA
    $91k-$129k(Glassdoor est.)
    NEW
    connectivity, discrete, SoC and custom devices. The company's products help engineers solve their unique design challenges in automotive… use of CAD tools. You will interact with other engineering teams such as Design, RnD, CAD, Tapeout and other. Responsibilities…
  • 4.0
    Apple – Santa Clara, CA
    5 days ago 5d
    40.00 Job Summary The SoC hardware development team is looking for an experience engineer to lead the implementation of low power… Experience in low power architecture, ASIC design implementation for low power, ASIC physicaldesign methodology. Experience with low…
  • 4.0
    Apple – Santa Clara, CA
    NEW
    thermal performance of packaging technologies Knowledge of SoCdesign methodology, low-power techniques and thermal analysis methods… package, PCB or mobile device design and thermal testing Experience working with IC physicaldesign parameters affecting electrical…
  • 2.7
    InvenSense – San Jose, CA
    $117k-$151k(Glassdoor est.)
    4 days ago 4d
    layout engineers on physicaldesign. Review layouts and provide feedback for optimal layout design. Tape-out designs on-schedule… leading provider of SoC platform solutions, we definitely want to hear from you. Description Design, implement and verify…
  • 4.0
    Apple – Santa Clara, CA
    $118k-$162k(Glassdoor est.)
    7 days ago 7d
    responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing state… with large SOCdesigns (>20M gates) with frequencies in excess of 1GHZ . Description Work with logic design team to understand…
  • 3.5
    Cavium, Inc. – San Jose, CA
    $87k-$113k(Glassdoor est.)
    8 days ago 8d
    Preferred/Plus: Experience in designing high-speed (>1 GHz) /high-performance embedded processor SOC products is a plus. Knowledge… As a new graduate engineer, you would contribute as a designengineer developing the next-generation of multi-core processors.…
  • 3.5
    Cavium, Inc. – San Jose, CA
    $163k-$217k(Glassdoor est.)
    26 days ago 26d
    10+ years of experience in RTL design of submicron SOC products (eg: Microprocessor based SOC’s). Experience in Micro-architecture… with the physicaldesign teams in aiding the implementation of the functional blocks. Requirements: Engineering degree required…
  • Avatar Integrated Systems – Santa Clara, CA
    $86k-$127k(Glassdoor est.)
    7 days ago 7d
    ASIC) and system on chip (SoC) design for advanced nodes (nanometers) processing, including the design and implementation of placement… Development) Engineer - Research, design and develop computer-aided very large scales integrated circuit (VLSI) physicaldesign and…
  • 3.7
    Intel – Santa Clara, CA
    $113k-$153k(Glassdoor est.)
    7 days ago 7d
    Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products… seeking an experienced structural physicaldesignengineer to work with a dynamic team designing Intel's next generation IP for High…
  • 3.5
    Cavium, Inc. – San Jose, CA
    $185k-$245k(Glassdoor est.)
    25 days ago 25d
    10+ years of experience in RTL design of submicron SOC products (eg: Microprocessor based SOC’s). Experience in Micro-architecture… Guide the physicaldesign teams in aiding the implementation of the functional blocks. Requirements: Engineering degree…
  • 4.4
    NVIDIA – Santa Clara, CA
    $134k-$177k(Glassdoor est.)
    Today 7hr
    world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development… Senior ASIC Floorplan DesignEngineer: NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world…
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