Verification Engineer Jobs in San Jose, CA | Glassdoor
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Verification Engineer Jobs in San Jose, CA

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  • 3.6
    Qualcomm – San Jose, CA
    Est. Salary $107k-$144k
    23 days ago 23d
    Job Id E1947330 Job Title Digital Verification Engineer Post Date 05/23/2017 Company - Division… Electrical Engineering or equivalent experience Preferred: Master's, Computer Science and/or Electrical Engineering or equivalent…
  • 4.2
    Intuitive Surgical – Sunnyvale, CA
    Est. Salary $87k-$120k
    10 days ago 10d
    We are seeking an engineer to play a key role in both simulation-based and in-system verification of our Field Programmable… using SystemVerilog Experience with an OVM or UVM-based verification environment preferred Python, TCL, and/or JavaScript…
  • 3.4
    Cavium, Inc. – San Jose, CA
    Est. Salary $96k-$132k
    2 days ago 2d
    memory coherency, memory ordering. Strong background in Soc verification methodology and test bench development using HVL such as… as Verilog, System Verilog, UVM and C/C++. Strong verification skills, understanding of methodology (object oriented programming…
  • 3.5
    Mobiveil – Milpitas, CA
    EASY APPLY
    Est. Salary $67k-$94k
    10 days ago 10d
    SOC/IP Functional Verification Experience Verification Expertise in System Verilog Expert in Verification methodologies (… LZ77 compression algorithm) Verification. Data compression Experince developing Verification components from scratch…
  • 3.7
    Intel – San Jose, CA
    Est. Salary $90k-$124k
    14 days ago 14d
    , or Computer Engineering - 10+ years of hands-on experience and a track-record of success in logic verification. 5 years of experience… Debugging failures to root causeMaintaining and enhancing the verification infrastructure by creating new tools to support validation.The…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $95k-$120k
    24 days ago 24d
    interacting with design engineers to identify important verification scenarios. Create a constrained-random verification environment using… with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and…
  • 3.8
    Vertisystem – Santa Clara, CA
    Est. Salary $59k-$83k
    30+ days ago 30d+
    the Pre-Silicon design verification team in verifying the core-level memory-subsystem blocks. The engineer will be responsible for…
  • 3.6
    Xilinx – San Jose, CA
    Est. Salary $83k-$116k
    24 days ago 24d
    / Medical (ISM) Wired Wireless Verification Engineer In this position, the candidate will be part of… Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is…
  • 3.5
    Broadcom – San Jose, CA
    Est. Salary $99k-$131k
    4 days ago 4d
    strong and expert level ASIC Verification Engineer in the area of PCIe SSD Controller verification working with the latest, greatest… / SoC verification using UVM, OVM or System Verilog. - Expertise in developing block level / system level verification environments…
  • 4.7
    Cypress HCM – Santa Clara, CA
    24 days ago 24d
    Design Verification Engineer The Design Verification Engineer is supporting our Client’s DNA Sequencing unit. You will be… creation, detailed verification of every aspect of the chip functionality including digital, DFT, and AMS verification. In addition…
  • Fungible – Santa Clara, CA
    Est. Salary $91k-$142k
    24 days ago 24d
    of the verification team, you will be responsible for independently creating leading-edge constrained-random verification environments… of experience in ASIC/SoC verification with SV/UVM environments In-depth knowledge of verification flows Clear understanding…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $100k-$137k
    9 days ago 9d
    people's lives by transforming mobility. As a Digital Verification Engineer, you will leverage your strong technical background… failure debug. Create verification infrastructure and tools. Identify and integrate third-party verification IP. Collect and analyze…
  • 3.7
    Axelon, Inc. – San Jose, CA
    Est. Salary $87k-$121k
    14 days ago 14d
    Job Title: Verification Engineer General Description Vision: Drive the functional verification of a new architecture GPU's… environments. Experience Requirements: Experienced with verification methodology such UVM/VMM/OVM. UVM is preferred. Successfully…
  • 4.0
    Cadence Design Systems – San Jose, CA
    Est. Salary $109k-$149k
    14 days ago 14d
    Principal Verification Engineer interested in challenging opportunities to be a technical verification lead in verification of complex… junior verification engineers Participate in ASIC and FPGA chip bringup on PCB and in systems Leverage verification tests for…
  • 3.1
    Integrated Device Technology – San Jose, CA
    Est. Salary $66k-$92k
    Today 9hr
    will contribute to implementation, modeling, emulation and verification of an embedded micro controller based SOC/mixed signal chip… must have strong knowledge of RTL design, simulation and verification test benches and be willing to work collaboratively to verify…
  • 3.7
    Axelon, Inc. – San Jose, CA
    Est. Salary $99k-$135k
    2 days ago 2d
    M.S. in Computer Engineering or Electrical Engineering • Prior Verification experience required • UVM verification experience highly… We are currently looking for a Senior ASIC/SoC Verification Engineer (Contract Position) to join our team in San Jose, CA. He…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $100k-$137k
    18 days ago 18d
    interacting with design engineers to identify important verification scenarios. Create a constrained-random verification environment using… with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and…
  • 3.5
    Mobiveil – Milpitas, CA
    EASY APPLY
    Est. Salary $67k-$94k
    9 days ago 9d
    of functional verification fundamentals encompassing state machine verification, complex protocol verification, functional test… strategies, directed and stress test generation, verification infrastructures and verification and/or debug flows In depth knowledge…
  • 3.5
    Synapse Design – San Jose, CA
    EASY APPLY
    Est. Salary $84k-$117k
    28 days ago 28d
    or similar language; Experience with constrain random verification methodology, such as UVM/OVM. 6+ years industry experience… Responsibilities: Work with RTL designer/system engineer define test plan according to system specification. Integrate RF behavior…
  • 3.8
    Infinera – Sunnyvale, CA
    Est. Salary $111k-$152k
    25 days ago 25d
    * Contribute significantly to verification infrastructure development. * Development of System Verilog/UVM based protocol/traffic…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $136k-$183k
    17 days ago 17d
    Responsible for verification of design, architecture, golden models and micro-architecture using advanced verification methodologies… the design and implementation, define the verification scope, develop the verification infrastructure (Transactors, Testbenches,…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $122k-$165k
    9 days ago 9d
    We are now looking for a Compiler Verification Engineer: What you’ll be doing: Compiler Test Development: Author/review test…
  • 4.8
    OSI Engineering – Sunnyvale, CA
    18 days ago 18d
    JOB DESCRIPTION: Verification Engineer in Sunnyvale, CA Must Have 3+ years of hands on experience in the following: • PCIe… assertions, test benches and score boarding for ASIC based verification Location: Sunnyvale, CA Type: Contract (3+ months)…
  • 3.5
    Mobiveil – Milpitas, CA
    EASY APPLY
    Est. Salary $67k-$94k
    24 days ago 24d
    Requirements: Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM Strong working experience in…
  • 1.7
    Pro Source Inc. – Livermore, CA
    EASY APPLY
    Est. Salary $73k-$104k
    1 days ago 24hr
    design and customer support activities as required. Verification engineers work closely with the support team and assist with customer… responsibilities include verification, including through development of test software on automated verification systems. Responsible…
  • 3.8
    Infinera – Sunnyvale, CA
    Est. Salary $93k-$129k
    4 days ago 4d
    is required. * 0 - 3 years of relevant experience in ASIC verification field. * Knowledge of System Verilog and scripting languages…
  • 2.6
    SK Hynix Memory Solutions – San Jose, CA
    Est. Salary $85k-$117k
    10 days ago 10d
    years experience in the field of Design Verification is a must Familiar with SoC verification skills including UVM and C-based test… bench. Develop and manage the sub-system and system level verification strategy and design for testing methodology Need to execute…
  • 3.9
    Apple Inc. – Cupertino, CA
    Est. Salary $108k-$149k
    10 days ago 10d
    As a member of design verification team, you will have the responsibility for construction of verification environment and coding… experience with Analog Assertion Based Verification ••Basic design background to analysis verification results ••Knowledge UVM-AMS is…
  • 4.6
    Macropace Technologies – Mountain View, CA
    Est. Salary $77k-$107k
    11 days ago 11d
    System Level Verification Mountain View, CA Full Time Position Job Description: Verilog and C/C++ coding a must… Makefiles, Perl scripting a must Chip/full system level ASIC Verification skills, and debug skills a must. Debug using waveforms a…
  • 2.7
    Microsemi – San Jose, CA
    Est. Salary $72k-$100k
    3 days ago 3d
    Experience with FPGA or ASIC design and verification tools, especially Formal Verification techniques Interest and/or experience… global organization Explore the application of Formal Verification techniques to validation of design implementations Develop…
  • 3.8
    Cisco Systems – San Jose, CA
    Est. Salary $98k-$124k
    3 days ago 3d
    in the lab. * Mentor and enable other engineers. * Lead and oversee design verification efforts of a cluster of blocks. Skills… Experience in high-performance ASIC verification. * Good understanding of ASIC design and verification methodologies and flows. * Hands-on…
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