ASIC Design Engineer Jobs in Santa Clara, CA | Glassdoor
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ASIC Design Engineer Jobs in Santa Clara, CA

  • 3.7
    Intel – San Jose, CA
    Est. Salary $93k-$138k
    11 days ago 11d
    Job Description As a member of the ASIC Frontend Design and Integration team, you will be part of Intel's Programmable Solution… Solution Group PSG, working on complex ASIC and FPGA designs in leading edge process nodes. Responsibilities include the following…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    Est. Salary $69k-$96k
    NEW
    Job Responsibilities The IC Design Team is searching for a ASICDesign Intern with general ASIC flow knowledge. Bilingual… and Korean General knowledge of ASIC flow from RTL to tape-out Work closely with the Design Verification team on functional verification…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $117k-$158k
    5 days ago 5d
    digital implementation and signoff flows Experienced with ASICdesign semi-custom and full-custom flow Hands-on experience running… the cutting edge processor design in deep submicron technologies, and on standard cell library design and characterization You'll…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $103k-$135k
    19 days ago 19d
    degree in Electrical Engineering or equivalent practical experience. Experience in software design and ASICdesign methodology development… installation/troubleshooting/debugging with vendors. As an ASICDesignEngineer on the chip implementation team, you will be responsible…
  • 3.9
    Cisco Systems – San Jose, CA
    NEW
    NPI to EOL. As a Cisco ASIC component engineer your tactical duties will bring together internal design/test/DFT teams with strategic… experience and skills to be a successful ASIC CE at Cisco: -BS Degree in Engineering with 10+ years of relevant hands-on experience…
  • 2.8
    cPacket Networks – San Jose, CA
    Est. Salary $87k-$117k
    7 days ago 7d
    expected to be able to design, implement and test both unit level modules and higher level architecture designs. Candidates should… should be comfortable understanding tradeoffs in the design and be able to articulate them. This role requires being able to develop…
  • 3.8
    Marvell Technology – Santa Clara, CA
    22 days ago 22d
    required. - A minimum 5 years of experience with digital ASICdesign, required. - Hands on experience with SOC verification… to observe the functionality of designs flow. We are looking for a Highly motivated engineer to join our team. - BS/MS in…
  • Fujitsu Network Communications – Sunnyvale, CA
    12 days ago 12d
    en/ We are seeking a seasoned Front-end DesignEngineer for our ASIC business unit. The primary responsibilities… customer design wins successfully. Support customer’s design through all phases of ASIC execution. Focus on design execution…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    Est. Salary $90k-$122k
    26 days ago 26d
    Digital Processor ASIC/FPGA Designer: The Staff ASIC/FPGA DesignEngineer will be working in the RF Center of Excellence (RF… effort to meet the customer requirements. The Staff FPGA/ASICdesigner will provide technical support across the enterprise as…
  • 3.4
    Advanced Micro Devices, Inc. – Sunnyvale, CA
    Est. Salary $104k-$141k
    4 days ago 4d
    Qualifications Education track for Electrical or Computer Engineering w/ focus on Computer/Graphics Architecture Must be proficient… Modeling (C / C++) Collaborate with Graphics Architects and Design & Verification Team to coordinate, participate in, new feature…
  • 3.9
    Cisco Systems – San Jose, CA
    7 days ago 7d
    ability to design and debug with minimal oversight. "Who You Are" You are an ASICDesign for Test engineer with 10+ years… Lead, ASICDesign for Test Location: San Jose, CA "Who You'll Work With" Our creative and talented team as Design for Test…
  • 3.4
    AMD – Sunnyvale, CA
    Est. Salary $88k-$120k
    4 days ago 4d
    team is looking for a Logic DesignEngineer who has experience working on complex IP/SOC Designs from concept to post silicon.… involved in: Designof IP micro-architectural level, making design trade-offs. Responsible for IP block level implementation…
  • 3.4
    Tektronix – Santa Clara, CA
    Est. Salary $104k-$137k
    18 days ago 18d
    The ASIC Mixed Signal engineer will be a member of the ASIC team in Santa Clara that interacts with Analog/circuit designers, digital… technologies. Circuit design experience of high performance analog products (High speed SAR ADCs) Experience with design of broadband,…
  • 3.6
    Broadcom – Santa Clara, CA
    Est. Salary $103k-$139k
    21 days ago 21d
    work with designengineers to verify fixes. ○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. ○… Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: ○ Architect block…
  • 2.8
    cPacket Networks – San Jose, CA
    Est. Salary $54k-$75k
    7 days ago 7d
    expected to be able to design, implement and test both unit level modules and higher level architecture designs. This role requires… be creating and implementing test plans for validating the design.…
  • 3.8
    Marvell Technology – Santa Clara, CA
    Est. Salary $102k-$128k
    13 days ago 13d
    timing simulation and verification, preparing design review. Work with testing engineer to evaluate, validate and debug silicon device… Responsible for design, development, modification and evaluation of high-speed digital circuit for signal processing components…
  • 3.1
    Toshiba – San Jose, CA
    Est. Salary $134k-$172k
    17 days ago 17d
    SATA SSD technologies prior to design. Will drive the development of the SSD Controller ASICdesign specification. Perform analysis… party IPs for SoC integation Drive SoC physical design implementation with ASIC vendor Work closely with Verification, Validation…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $129k-$193k
    5 days ago 5d
    leading high performance low power cache designs Manage a talented high powered ASICdesign team through career growth Lead the… Senior ASICDesign Manager - Cache Subsystem Job Number: 112919812 Santa Clara Valley, California, United States Posted…
  • 3.8
    Marvell Technology – Santa Clara, CA
    Est. Salary $94k-$119k
    22 days ago 22d
    closure. * MS in EE with 3 years of work experience in SOC/ASIC/IP development. * Must have knowledge and experience of HDL… Knowledge of UVM and System Verilog is required. * Background in ASIC implementation including lint, CDC, synthesis, formal and static…
  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $113k-$153k
    7 days ago 7d
    Experience in high-performance ASIC verification. Good understanding of ASICdesign and verification methodologies and flows… collaboration with design, software and hardware teams to ensure a successful product delivery. Mentor and enable other engineers. Skills…
  • 3.8
    Marvell Technology – Santa Clara, CA
    Est. Salary $73k-$98k
    22 days ago 22d
    stages of ASICdesign flows, and is experienced with state-of-the-art design tools. The candidate is strong in logic design and verification… Provide design documentation, description and information to application engineers, field application engineers, test engineers, production…
  • 3.4
    AMD – Sunnyvale, CA
    Est. Salary $104k-$141k
    20 days ago 20d
    relevant automation. Enable efficient support of multiple large engineering projects simultaneously Experience in development flows… collaboration skills. Experience working in large multi-site engineering organizations Demonstrated ability to work cross-functionally…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    Est. Salary $89k-$119k
    26 days ago 26d
    Digital Processor ASIC/FPGA Designer: The Senior ASIC/FPGA DesignEngineer will be working in the RF Center of Excellence (… (RF CoE). The Senior FPGA/ASICdesigner will provide technical support to the RF COE ASIC/FPGA design Team. The individual…
  • 3.1
    Rambus – Sunnyvale, CA
    Est. Salary $101k-$138k
    6 days ago 6d
    teams including ASICdesignengineers and architects, other verification engineers and system test engineers, security experts… Design and implement verification test plans, testbenches, infrastructure and platforms Work with ASICdesigners and architects…
  • 3.4
    Advanced Micro Devices, Inc. – Sunnyvale, CA
    Est. Salary $102k-$139k
    28 days ago 28d
    KEY RESPONSIBILITIES Work in a team of design verification and designengineers, involved in all aspects of the verification… REQUIREMENTS Required: Bachelor's, Computer Engineering and/or Electrical Engineering #LI-PS1 Requisition Number: 37921…
  • 4.4
    Embedded Resource Group – Mountain View, CA
    25 days ago 25d
    ASIC/FPGA Design Verification Engineer Seeking design verification engineer for verification of FPGA design.… Job Requirements Required Skills: ASIC or FPGA design verification At least 2 + UVM projects in past System…
  • 4.0
    Nokia – Sunnyvale, CA
    12 days ago 12d
    conventional design techniques. As a Senior Engineer, 5G ASICDesign, you will effectively communicate your design ideas to fellow… wireless communications! We are now looking for Senior Engineer, 5G ASICDesign to join our team. Key responsibilities In this…
  • 3.3
    Sony Electronics – San Jose, CA
    Est. Salary $90k-$124k
    21 days ago 21d
    and design. Sony Electronics, a global leader in image sensors, is seeking a staff VLSI/ASIC logic DesignEngineer to work… then develop and implement solutions Familiarity with ASIC/SoC design/verification methodologies Ability to write detailed…
  • 2.9
    Toshiba America Electronic Components – San Jose, CA
    Est. Salary $115k-$156k
    4 days ago 4d
    verification platform Requirements: 7+ years of SoC/ASIC verification experience Hands on experience using UVM SSD… development of a verification plan, in collaboration with the design and architecture teams, the definition and implementation of…
  • 3.7
    Qualcomm – San Jose, CA
    Est. Salary $102k-$131k
    12 days ago 12d
    protocol. The role of an wireless ASICdesignengineer at Qualcomm is the specification, design, verification and implementation… Job Id E1956136 Job Title Wi-Fi ASICDesignEngineer Post Date 07/25/2017 Company Division Qualcomm…
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