ASIC Design Engineer Jobs in Santa Clara, CA | Glassdoor
  • All Jobs (417)

ASIC Design Engineer Jobs in Santa Clara, CA

Filters
Filters
  • Approgence – Santa Clara, CA
    Est. Salary $85k-$114k
    12 days ago 12d
    lower level design experience of multi-million gate ASICs in advance process nodes 5+ years experience designing cellular modem… Designing high performance signal processing engines. Designing custom instruction-set architectures Designing instruction…
  • 3.9
    Synaptics – San Jose, CA
    Est. Salary $90k-$123k
    5 days ago 5d
    Responsibilities The IC Design team is searching for a hands-on, team oriented, ASICdesignengineer with strong digital design expertise.… . In this role, the engineer will be responsible for the design of digital blocks and sub-systems that implement innovative touch…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $82k-$127k
    6 days ago 6d
    -based infrastructure solutions Experience supporting ASICengineering workflows and EDA tools Knowledge of network dedicated… Science, Electrical Engineering or related field. ) and minimum 7 plus years experience leading, designing and operating large…
  • 3.6
    Broadcom – Santa Clara, CA
    Est. Salary $110k-$141k
    11 days ago 11d
    networking ASIC is a plus. Working in SOC with frequencies more that 1GHz is an advantage. Work effectively with design verification… verification engineers to recommend and help develop verification and test strategies for various design blocks, and will also work closely…
  • 3.6
    Qualcomm – Santa Clara, CA
    Est. Salary $98k-$124k
    13 days ago 13d
    periphery circuitry design including MUXs and row drivers Fluent in overall system simulations (Sensor / ASIC) and interactions… periphery circuitry design including MUXs and row drivers Fluent in overall system simulations (Sensor / ASIC) and interactions…
  • 3.9
    Cisco Systems – San Jose, CA
    4 days ago 4d
    As a Design Verification Engineer you will work with the ASICdesign and verification teams to develop next generation ASICs for… forwarding was performed in dedicated ASICdesigns. These days we are looking to make those ASICs more general and programmable. P4…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $118k-$161k
    6 days ago 6d
    Work closely with Architecture, ASIC, Mixed Signal, Package, and PCB Design teams to design and ensure link performance meets… experience with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes…
  • 3.7
    Intel – San Jose, CA
    Est. Salary $93k-$138k
    9 days ago 9d
    Job Description As a member of the ASIC Frontend Design and Integration team, you will be part of Intel's Programmable Solution… Solution Group PSG, working on complex ASIC and FPGA designs in leading edge process nodes. Responsibilities include the following…
  • 3.9
    Synaptics – San Jose, CA
    22 days ago 22d
    applicants to apply for a career opportunity as a Senior Staff ASIC Architect in our Platform Architecture department. This is an… architectures for the next-generation of touch-sensing and fingerprint ASIC’s. A solid understanding of analog and digital circuitry is required…
  • 3.6
    Broadcom – Santa Clara, CA
    Est. Salary $118k-$150k
    17 days ago 17d
    work with designengineers to verify fixes. Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. Replicate… and other new initiatives by working on design verification. As a verification engineer, your responsibilities will include:…
  • 3.5
    Samsung Semiconductor, Inc. – San Jose, CA
    NEW
    and initiatives through feasibility, FPGA prototyping and ASICdesign Supervise verification contractors and oversee the verification… JOB TITLE Logic Design and Hardware Architecture Lead Engineer Requisition ID DSA31141 OVERVIEW Samsung…
  • 3.4
    Micron – Milpitas, CA
    14 days ago 14d
    Computer Engineering/Electrical Engineering. Minimum Experience : 5 years with Atleast 3 years in ASICDesign Position is not open… Req. ID: 84603 Engineers in the ASIC Architecture Group have the rare opportunity to transform their creative ideas into best…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $102k-$146k
    6 days ago 6d
    doing: Drive physical design and timing convergence of high-frequency low-power CPU, GPU, and/or ASIC at block level, cluster… and hands-on skills in RTL/Logic design for timing closure desired. Knowledge in physical design and optimization e.g. placement…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $100k-$127k
    NEW
    microcontroller. You will work with the designengineers to ensure correct understanding of design and its environment. You will work… Qualifications Minimum qualifications: 2 years of ASIC digital verification experience, including SystemVerilog, testbenches…
  • 3.8
    Marvell Technology – Santa Clara, CA
    Est. Salary $95k-$127k
    19 days ago 19d
    language like PERL/Python, TCL & C/C LINT/CDC Familiarity of ASICdesign flow SSD controller architecture NVMe protocol knowledge… Perform functional verification of design on block and system level. Provide design documentation, description and information…
  • 3.7
    Intel – Santa Clara, CA
    Est. Salary $88k-$123k
    15 days ago 15d
    Frontend Design Automation Engineer, you will be responsible for driving methodology, and productivity improvements in design flows… team, we are looking for a senior level Front End Design Automation Engineer to join the 5G Mobile Wireless Technology Development…
  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $97k-$139k
    5 days ago 5d
    such as DCBX/PFC, NIV/802.1BR, QoS, L2/L3 switching, forwarding ASICs, ACL, SPAN/ERSPAN, tunneling, L4-L7 networking protocols or… with the Cisco UCS VIC adapter software development team to design and implement I/O solutions for the UCS product family deployments…
  • 3.5
    QuickLogic – Sunnyvale, CA
    Est. Salary $118k-$155k
    NEW
    digital simulator such as VERILOG Highly Desirable: ASICdesign experience Product development experience CAD experience… Posted On06/22/2017 Senior Staff, DesignEngineer Sunnyvale Salary Range : Worker Category…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $127k-$168k
    4 days ago 4d
    years of embedded software design experience 3+ years of industry experience in ARM based ASIC / SoC Design Verification (DV) Knowledgeable… SoC Embedded Software Engineer Job Number: 57495882 Santa Clara Valley, California, United States Posted: Aug. 18, 2017…
  • 3.8
    Synopsys – Mountain View, CA
    Est. Salary $96k-$130k
    20 days ago 20d
    Job Category Engineering Hire Type Employee Job Description and Requirements FPGA/ASIC Hardware DesignEngineer As part of… UVM) (Highly desired). Good knowledge of ASIC/FPGA design flow and circuit design principles. Knowledge and experience in mixed-signal…
  • 3.7
    Xilinx – San Jose, CA
    Est. Salary $88k-$133k
    13 days ago 13d
    hardware (ASIC) Implementation of complex signal processing on at least one of the following platforms: FPGAs, ASIC, ASSP, GPP… desirable. Experience with the software and/or hardware (e.g. ASIC) realization of these algorithms is highly valuable. Ability…
  • 3.1
    Avago Technologies – Santa Clara, CA
    Est. Salary $104k-$138k
    11 days ago 11d
    networking ASIC is a plus. Working in SOC with frequencies more that 1GHz is an advantage. Work effectively with design verification… verification engineers to recommend and help develop verification and test strategies for various design blocks, and will also work closely…
  • 3.7
    Xilinx – San Jose, CA
    Est. Salary $122k-$179k
    13 days ago 13d
    algorithms for ASICs and/or FPGAs. Expert with C , data structures, algorithms and its application to electronic design automation… software engineer to be part of the Xilinx Vivado Physical Implementation team. This team is responsible for design, implementation…
  • 3.5
    Mobiveil – Milpitas, CA
    EASY APPLY
    Est. Salary $65k-$89k
    6 days ago 6d
    -architecture of complex IP and/or ASIC blocks Experience creating Verilog based designs from Scratch Experience developing…
  • 3.9
    Nokia – Sunnyvale, CA
    10 days ago 10d
    blocks Knowledge with digital ASIC physical design flows. Knowledge of digital ASIC RTL design flow. Experience with mixed-… wireless communications! We are now looking for R&D manager, 5G ASIC integration to join our team. Key responsibilities In this…
  • 3.7
    Oclaro – San Jose, CA
    Est. Salary $115k-$167k
    30+ days ago 30d+
    Commodity Manager ASICs Oclaro, Inc. (Nasdaq: OCLR), is a leader in optical components, modules and subsystems for the core… Management team responsible for the strategic direction of the ASICs commodity. As such, this position will "own" the commodity and…
  • 3.4
    Micron Technology, Inc. – Milpitas, CA
    Est. Salary $80k-$108k
    7 days ago 7d
    mixed-mode design and validation. Knowledge of UVM and System Verilog is desirable. Knowledge of Digital ASICDesign methodology… Req. ID: 91141 The DesignEngineer Intern in the FLASH Group at Micron Technology, Inc., will be core technical individual…
  • 3.6
    Redolent, Inc – Sunnyvale, CA
    Est. Salary $65k-$83k
    11 days ago 11d
    verification is a plus. Strong understanding of different phases of ASIC and/or full custom chip development is required. Experience… requirement with our direct client: Title: Design Verification Engineer Location: Sunnyvale, CA Duration: 6 to 12+ months…
  • 4.0
    Roche – Santa Clara, CA
    Est. Salary $105k-$133k
    28 days ago 28d
    degree in EE/CS with 10+ years of industry experience in ASIC / FPGA design verification Hands-on experience in the entire verification… Block level and System level tests writing for FPGA / ASICdesigns Experience with code coverage methodology Domain expertise…
  • 3.3
    Omnivision Technologies, Inc – Santa Clara, CA
    Est. Salary $103k-$139k
    27 days ago 27d
    production, to customer support. In-depth hands-on experience in ASICdesign flow: RTL coding, simulation, synthesis, static timing analysis… timing control design and verification. Chip bring-up, validation, and debugging. Customer and application engineer (AE) support…
  • 3.8
    Marvell Technology – Santa Clara, CA
    Est. Salary $105k-$140k
    6 days ago 6d
    § Verify large ASIC blocks such as PCIe/Main Fabric/AXI independently and rapidly. § 6 years of ASIC Verification Experience… performing the functional and gate level verification of the ASICs. Define, architect, code, and deliver verification suites…
Page 5 of 14
Unlock Your Free Employer Account