ASIC Design Verification Engineer Jobs in Santa Clara, CA | Glassdoor
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ASIC Design Verification Engineer Jobs in Santa Clara, CA

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  • 3.3
    Calsoft Labs Inc. – Santa Clara, CA
    Est. Salary $97k-$124k
    24 days ago 24d
    Experience: See below Education: See below ASICDesignVerificationEngineers, Santa Clara, CA. Exp in System Verilog, OVM, UVM,… ASICDesignVerification EngineersCompany: Calsoft Labs Inc. Location: Santa Clara, CA Position Type: Full Time Experience…
  • 4.4
    VeriSilicon Holdings Co., Ltd. – San Jose, CA
    EASY APPLY
    Est. Salary $89k-$120k
    NEW
    familiar with all stages of the ASICdesign flow (including specification, architecture, and design implementation) Highly motivated… Verilog), and verification. Expected skills: 5+ years hands-on experience with focus on front-end complex RTL design Programming…
  • 4.5
    Technology Search International – Santa Clara, CA
    Est. Salary $92k-$118k
    18 days ago 18d
    Opportunity for an experienced ASICVerificationEngineer who has experience with SoCs and ASICs and verifying data center & communication… fantastic highly programmable ASICs. Requirements: 8+ years of ASIC / SoC Verification experience with SV/UVM environments…
  • 3.7
    Infinera – Sunnyvale, CA
    Est. Salary $137k-$176k
    1 days ago 22hr
    impact on internal designs and architecture. Micro-architecture and design of ASIC/FPGA: Includes design documentation, review… of experience in ASICDesign. Participation in at least 1 full ASIC cycle as a designer from Arch to Bringup Good knowledge and…
  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $113k-$153k
    1 days ago 20hr
    Experience in high-performance ASICverification. Good understanding of ASICdesign and verification methodologies and flows.… one of our switches. Who You Are You are an ASICverificationengineer that will Contribute in micro-architecture…
  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $113k-$153k
    NEW
    Experience in high-performance ASICverification. Good understanding of ASICdesign and verification methodologies and flows.… collaboration with design, software and hardware teams to ensure a successful product delivery. Mentor and enable other engineers. Skills…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $142k-$190k
    NEW
    for a Senior ASICVerificationEngineer: NVIDIA is seeking elite ASICVerificationEngineers to verify the design and implementation… responsible for verification of the ASICdesign, architecture, golden models and micro-architecture using advanced verification methodologies…
  • 4.0
    Axelon, Inc. – San Jose, CA
    Est. Salary $99k-$135k
    1 days ago 19hr
    We are currently looking for a Senior ASIC/SoC VerificationEngineer (Contract Position) to join our team in San Jose, CA. He… and compute ASIC/ FPGA and system solutions. The ideal candidate must have prior experience developing Verification architecture…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $98k-$123k
    23 days ago 23d
    interacting with designengineers to identify important verification scenarios. Create a constrained-random verification environment… with designengineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes…
  • 3.1
    Rambus – Sunnyvale, CA
    Est. Salary $101k-$138k
    1 days ago 1d
    teams including ASICdesignengineers and architects, other verificationengineers and system test engineers, security experts… Design and implement verification test plans, testbenches, infrastructure and platforms Work with ASICdesigners and architects…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $142k-$190k
    NEW
    for a Senior ASICVerificationEngineer: NVIDIA is seeking an elite ASICVerificationEngineer to verify the design and implementation… working on verifying ASICdesign using advanced verification methodologies. You are expected to understand the design and verify correctness…
  • 3.7
    Xilinx – San Jose, CA
    Est. Salary $108k-$136k
    28 days ago 28d
    Wireless FDST Verification group is looking for a Senior DesignVerificationEngineer to contribution on FPGA block… full chip verification. The individual will help design, develop and use simulation and/or formal based verification environments…
  • 3.8
    Marvell Technology – Santa Clara, CA
    17 days ago 17d
    years of experience with digital ASICdesign, required. - Hands on experience with SOC verification using UVM and C. - Experience… functionality of designs and developing corresponding verification plans. Designing and developing components of our verification environment…
  • 4.4
    Embedded Resource Group – Mountain View, CA
    21 days ago 21d
    ASIC/FPGA DesignVerificationEngineer Seeking designverificationengineer for verification of FPGA design.… Job Requirements Required Skills: ASIC or FPGA designverification At least 2 + UVM projects in past System Verilog…
  • 3.0
    Aquantia – San Jose, CA
    EASY APPLY
    Est. Salary $79k-$99k
    20 days ago 20d
    understanding of digital designverification methodologies and tools including: • Expertise in creating verification infrastructure using… Responsibilities: • Responsible to define and implement verification architectures for mixed signal data communications semiconductors…
  • 3.8
    Marvell Technology – Santa Clara, CA
    Est. Salary $94k-$119k
    17 days ago 17d
    closure. * MS in EE with 3 years of work experience in SOC/ASIC/IP development. * Must have knowledge and experience of HDL… Knowledge of UVM and System Verilog is required. * Background in ASIC implementation including lint, CDC, synthesis, formal and static…
  • 3.9
    Ambarella – Santa Clara, CA
    Est. Salary $89k-$116k
    6 days ago 6d
    micro-architecture specifications. Logic design, implementation, and verification using Verilog, System Verilog, and any required… SystemVerilog, Verilog, Perl, and C/C++. Knowledge of designverification, and functional coverage. Ability to program scripting…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    Est. Salary $113k-$154k
    NEW
    Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business… technical oversight. Basic Qualifications FPGA & ASICVerification experience. Language Proficient in VHDL/Verilog for…
  • 3.2
    Seagate Technology – Fremont, CA
    Est. Salary $94k-$128k
    9 days ago 9d
    Experience with advance ASICdesignverification methodology such as UVM and VMM flow. Experience with all popular ASIC EDA tools like… solutions innovation, seeks a Design and VerificationEngineer for an exciting role at our new Freemont Design Center. You will help us…
  • 4.3
    Quanergy – Sunnyvale, CA
    Est. Salary $83k-$108k
    1 days ago 20hr
    Digital ASICDesignEngineer-17040008 Location: Sunnyvale, California, United States Full-time The Digital ASIC Design… characterize/test the performance of the designedASIC, and work to integrate the design into our LiDAR sensors. A successful…
  • 3.7
    Fortinet – Sunnyvale, CA
    Est. Salary $87k-$115k
    13 days ago 13d
    Description Fortinet ASICdesign team is looking for a top computer engineering or electrical engineering graduate with an interest… member of the ASICdesign team, you will help design Fortinet’s next generation Network Processor and System-On-Chip ASIC to accelerate…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $99k-$130k
    7 days ago 7d
    collaborating with other architects, ASICdesigners and verificationengineers to design high frequency clocks. You should be… today. The GPU clocks group is looking for a top-notch ASICengineer to join the team. The Team is responsible for crafting all…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $110k-$154k
    10 days ago 10d
    Architecture, Designverification, Physical Design, DFT, and power teams to achieve first tapeout success on designs 3) Develop… aspects of development design for large SOC blocks including: Internal and external IP integration, design of system bus and control…
  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $104k-$144k
    NEW
    Title: ASIC Physical DesignEngineer Location: San Jose, CA WHO YOU'LL WORK WITH: Our creative and talented team as Physical… Physical Design lead in San Jose, CA. You will work with ASIC Front-end teams to understand chip architecture and drive physical…
  • 2.8
    cPacket Networks – San Jose, CA
    Est. Salary $83k-$115k
    NEW
    troubleshoot issues in the design. This role may also require creating behavioral models of the design and developing RTL which… candidates to develop and integrate the current and future RTL designs into a UVM environment. Candidates will need to create reports…
  • 3.1
    Toshiba – San Jose, CA
    Est. Salary $138k-$186k
    12 days ago 12d
    to the verification plan Work closely with Design & Firmware teams to resolve hardware issues Validate SoC design in FPGA… in managing & leading a HW verification team. Education MSEE or PhD in Electrical Engineering or Computer Science…
  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $101k-$127k
    NEW
    Experience in high-performance ASICverification. Good understanding of ASICdesign and verification methodologies and flows.… Participate in the architecture and verification of complex, high-performance, and highly integrated ASICs used in Cisco's networking products…
  • 4.6
    TalentBurst – Santa Clara, CA
    6 days ago 6d
    include developing the verification environment; developing test plans and verifying the function of the ASIC/FPGA at both the full… experience, with several complete and successful FPGA design/verification cycles under his/her belt Strong SystemVerilog/UVM,…
  • 3.3
    Omnivision Technologies, Inc – Santa Clara, CA
    Est. Salary $106k-$145k
    NEW
    with C model engineers to build bit-accurate C model for 265 video encoder hardware verification. Ensure that design implementations… architecture designs and implementations for H.264 hardware encoder, rate control for video coding, RTL verification and Verilog…
  • 3.8
    Marvell Technology – Santa Clara, CA
    Est. Salary $87k-$110k
    8 days ago 8d
    timing verification, power analysis, power domain control, supporting P&R, design rule checks RTL design and give design review… review. Work with testing engineer to evaluate, validate and debug silicon device. Work with technique writter on user specification…
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