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ASIC Physical Design Engineer Jobs in Santa Clara, CA

106Jobs

  • 4.4
    ConnectTel, Inc. – Sunnyvale, CA
    25 days ago 25d
    Our client is looking for AsicPhysicalDesign Place and Route Engineers for its Sunnyvale, CA location. Estimated Contract… Required Skills: Over 6 years experience in ASICPhysicalDesign from RTL to GDSII. Excellent analytical and problem…
  • 3.4
    Sony Electronics – San Jose, CA
    $95k-$130k(Glassdoor est.)
    27 days ago 27d
    style and design. Sony Electronics, a global leader in image sensors, is seeking a staff VLSI/ASIC logic DesignEngineer to work… then develop and implement solutions Familiarity with ASIC/SoC design/verification methodologies Ability to write detailed…
  • 3.9
    Cohere Technologies, Inc – Santa Clara, CA
    NEW
    directly to the VP of Engineering. Required Qualifications: 5+ years of experience managing an ASICdesign team, with demonstrated… sized teams Must have experience in ASIC vendor management related to package design, SI analysis, silicon testing, characterization…
  • 3.8
    Fortinet – Sunnyvale, CA
    $150k-$195k(Glassdoor est.)
    HOT
    Requirement MS & BS in Electrical Engineering or related field with 7+ years of SOC ASICdesign experience. #GD #LI-EL1 FTNT… challenging schedules, lead design teams through various phases of ASICdesign process including RTL design, chip level verification…
  • Approgence – San Jose, CA
    $83k-$117k(Glassdoor est.)
    18 days ago 18d
    Job Title : ASICPhysicalDesignEngineer Job Location : San Diego & San Jose, CA Job Description : This person will… complete physicaldesign. He will identify physicaldesign issues in early stage, working with RTL engineer to fix. He will isolate…
  • ASICSoft, Inc. – Sunnyvale, CA
    22 days ago 22d
    Looking for ASICPhysicaldesignengineer to work at our client location for a contract period. KEY RESPONSIBILITIES:… solutions REQUIREMENTS: Over 6 years experience in ASICPhysicalDesign from RTL to GDSII Excellent analytical and problem…
  • 3.6
    Software Galaxy Systems, LLC – Sunnyvale, CA
    $77k-$108k(Glassdoor est.)
    17 days ago 17d
    ASICPhysicalDesign Place and Route Engineer Location: Sunnyvale, CA 94088 Pay Rate: $60-$90/hour W2 (Depending on Experience… REQUIREMENTS: Over 6 years’ experience in ASICPhysicalDesign from RTL to GDSII Excellent analytical and problem…
  • 4.0
    Apple – Santa Clara, CA
    $112k-$156k(Glassdoor est.)
    27 days ago 27d
    ASICDesign Integration Engineer Job Number: 52280683 Santa Clara Valley, California, United States Posted: Oct. 2, 2017… quality design. Key Qualifications This position requires thorough knowledge of the ASICdesign flow, FE and Design verification…
  • 4.0
    Cadence Design Systems Inc. – San Jose, CA
    $126k-$169k(Glassdoor est.)
    7 days ago 7d
    technology team responsible for research and development of these ASICengines and how they work as a system to reprogrammably emulate customers… or Computer Engineering, graduate level or compensating experience. Proven success in development of complex ASIC, FPGAs and…
  • 4.0
    Apple – Santa Clara, CA
    $122k-$154k(Glassdoor est.)
    5 days ago 5d
    Knowledge of all aspects of ASICphysicaldesign. Scripting skills to debug flow related issues and make enhancements as appropriate.… PhysicalDesign Verification Engineer Job Number: 32821198 Santa Clara Valley, California, United States Posted: Sep. 1…
  • 3.7
    Marvell Technology – Santa Clara, CA
    7 days ago 7d
    Responsibilities:  Responsible for design, verification, implementation (ASIC) for high-performance, physical layer, high speed wired data… and in-depth knowledge of ASICdesign flows.  Familiar with reusable HDL coding styles and design for high volume manufacture…
  • Avatar Integrated Systems – Santa Clara, CA
    $68k-$101k(Glassdoor est.)
    5 days ago 5d
    degree in Electrical Engineering with coursework in VLSI Design, CMOS digital circuits, ASIC CMOS Design, Total Quality Management… Application Engineer - Santa Clara, CA Application Engineer: Participate at the design, implementation and support of…
  • 4.1
    TEEMA Solutions Group – Sunnyvale, CA
    19 days ago 19d
    Category: Engineering | Job Type: Contract Apply Now! ASICPhysicalDesign Place and Route Engineer KEY RESPONSIBILITIES… website at www.teemagroup.com | ASICPhysicalDesign Place and Route Engineer x5 Sunnyvale, California, United States…
  • Avatar Integrated Systems – Santa Clara, CA
    $86k-$127k(Glassdoor est.)
    5 days ago 5d
    integrated circuits (ASIC) and system on chip (SoC) design for advanced nodes (nanometers) processing, including the design and implementation… Development) Engineer - Research, design and develop computer-aided very large scales integrated circuit (VLSI) physicaldesign and…
  • 4.0
    Apple – Santa Clara, CA
    $112k-$156k(Glassdoor est.)
    NEW
    of SoC ASICDesign. Understanding of RTL Logic Design, Synthesis, DFT, STA, SOC/ASICDesign Flows, and PhysicalDesign Implementation… ECO Design Integration Engineer Job Number: 99742204 Santa Clara Valley, California, United States Posted: Jul. 31, 2017…
  • 4.0
    Apple – Santa Clara, CA
    $106k-$144k(Glassdoor est.)
    6 days ago 6d
    quality design. Key Qualifications This position requires thorough knowledge of the ASICdesign flow, FE and Design verification… least 5+ years experience in ASICdesign flow •Proven track record of high performance designs in high volume production for…
  • 4.0
    Apple – Santa Clara, CA
    $106k-$144k(Glassdoor est.)
    NEW
    IP/SoC design: Previous experience in multimedia IP design and integration. Industry exposure to and knowledge of ASIC/FPGA design… As a senior IP Designengineer you will have responsibilities spanning all aspects of multimedia IP design: Will be responsible…
  • 4.0
    Apple – Santa Clara, CA
    $83k-$115k(Glassdoor est.)
    NEW
    definition, specification, design, simulation and unit level verification of digital functions on Mixed Signal ASICs. Key Qualifications… Supporting all design integration activities like Lint, CDC, Synthesis & ECO •Working with PhysicalDesign Team on STA, physical, power…
  • 3.9
    Cisco Systems – San Jose, CA
    $116k-$157k(Glassdoor est.)
    HOT
    state-of-the-art design, verification and physicaldesign methodologies created by one of the most advanced ASIC teams in the world… phase of the ASIC development process from architecture definition, implementation, verification, physicaldesign, lab bring-up…
  • 3.6
    Redolent, Inc – San Jose, CA
    EASY APPLY
    $61k-$86k(Glassdoor est.)
    18 days ago 18d
    following urgent need with our client Title - RTL DesignEngineer (ASIC/FPGA any one) Duration - Full Time Location - San… RTL DesignEngineer with WI-FI domain. Solid understanding of fundamentals of wireless communication physical and MAC…
  • 4.0
    Apple – Santa Clara, CA
    $127k-$193k(Glassdoor est.)
    NEW
    + years of work experience.   RTL Logic Design experience of multi-million gate ASICs   Hands on experience for all aspects of… on high speed, low power designs   Experience in synthesis flows, DFT and power synthesis, physical synthesis   • Experience…
  • 4.0
    Apple – Santa Clara, CA
    $140k-$211k(Glassdoor est.)
    NEW
    10+ years of work experience. •RTL Logic Design experience of multi-million gate ASICs •Hands on experience for all aspects of… power designs •Experience in synthesis flows, DFT and power synthesis, physical synthesis •Experience in low power design and…
  • 3.6
    Broadcom – Santa Clara, CA
    $109k-$141k(Glassdoor est.)
    17 days ago 17d
    As a member of the ASIC Implementation team, you will be part of the team implementing new technologies in a variety of exciting… Closure · Working independently with the PNR & RTL design team on Physical implementation and Power-intent requirements Requirement…
  • 3.8
    Xilinx – San Jose, CA
    $127k-$185k(Glassdoor est.)
    12 days ago 12d
    Familiar with state of the art placement/routing/physical synthesis algorithms for ASICs and/or FPGAs. Expert with C , data structures… Vivado Physical Implementation team. This team is responsible for design, implementation, analysis and test of FPGA physical implementation…
  • 4.0
    Apple – Santa Clara, CA
    $116k-$161k(Glassdoor est.)
    NEW
    definition, specification, design, simulation and unit level verification of digital functions on Mixed Signal ASICs. Key Qualifications… Job Summary As a digital IC DesignEngineer, the individual’s primary responsibility will be RTL design. This will include block/…
  • 3.5
    Cavium, Inc. – San Jose, CA
    $87k-$113k(Glassdoor est.)
    6 days ago 6d
    You will work directly with senior members of the ASIC team to learn and design state of art high speed digital systems. Responsibilities… As a new graduate engineer, you would contribute as a designengineer developing the next-generation of multi-core processors.…
  • 4.0
    Apple – Santa Clara, CA
    $101k-$139k(Glassdoor est.)
    5 days ago 5d
    years experience in hierarchical ASIC P&R and flow development. Experience with all aspects of ASIC PD including floorplanning, power-distribution… to improve quality of physicaldesign. Work with chip design teams to implement and customize design flows that are optimal…
  • 4.0
    Cadence Design Systems – San Jose, CA
    $77k-$108k(Glassdoor est.)
    NEW
    technology team responsible for research and development of these ASICengines and how they work as a system to reprogrammably emulate customers… or Computer Engineering, graduate level or compensating experience. Proven success in development of complex ASIC, FPGAs and…
  • 4.0
    Apple – Santa Clara, CA
    5 days ago 5d
    years experience in hierarchical ASIC P&R and flow development. Experience with all aspects of ASIC PD including floorplanning, power-distribution… solutions to improve quality of physicaldesign. Work with chip design teams to implement and customize design flows that are optimal for…
  • 4.4
    Google – Mountain View, CA
    $106k-$141k(Glassdoor est.)
    25 days ago 25d
    degree in Electrical Engineering or equivalent practical experience. Experience in software design and ASICdesign methodology development… installation/troubleshooting/debugging with vendors. As an ASICDesignEngineer on the chip implementation team, you will be responsible…
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