ASIC Verification Engineer Jobs in Santa Clara, CA | Glassdoor
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ASIC Verification Engineer Jobs in Santa Clara, CA

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  • 3.8
    Infinera – Sunnyvale, CA
    Est. Salary $93k-$129k
    9 days ago 9d
    EE is required. * 0 - 3 years of relevant experience in ASIC verification field. * Knowledge of System Verilog and scripting languages…
  • 3.8
    Axelon, Inc. – San Jose, CA
    Est. Salary $99k-$135k
    7 days ago 7d
    We are currently looking for a Senior ASIC/SoC Verification Engineer (Contract Position) to join our team in San Jose, CA. He… and compute ASIC/ FPGA and system solutions. The ideal candidate must have prior experience developing Verification architecture…
  • 3.5
    Broadcom – San Jose, CA
    Est. Salary $99k-$131k
    9 days ago 9d
    a strong and expert level ASIC Verification Engineer in the area of PCIe SSD Controller verification working with the latest, greatest… / SoC verification using UVM, OVM or System Verilog. - Expertise in developing block level / system level verification environments…
  • 4.4
    Embedded Resource Group, Inc. – San Jose, CA
    30+ days ago 30d+
    ASIC Verification Engineer ASIC verification for SSD controller System-on-Chip. Participate in definition and the deployment… tests. Required Skills: 3-10 years experience in ASIC verification UVM and SystemVerilog Desired Skills: PCIe…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $95k-$120k
    1 days ago 1d
    interacting with design engineers to identify important verification scenarios. Create a constrained-random verification environment using… with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and…
  • 3.8
    Infinera – Sunnyvale, CA
    Est. Salary $111k-$152k
    2 days ago 2d
    development and execution of self-checking tests for complex digital ASICs. Infinera is an equal opportunity employer. All qualified… * Contribute significantly to verification infrastructure development. * Development of System Verilog/UVM based protocol/traffic…
  • 3.8
    Cisco Systems – San Jose, CA
    Est. Salary $108k-$147k
    9 days ago 9d
    enable other engineers. Skills Required: Experience in high-performance ASIC verification. Good understanding… understanding of ASIC design and verification methodologies and flows. Hands-on experience with HVL and HDL languages and tools…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $136k-$183k
    5 days ago 5d
    looking for a Senior ASIC Verification Engineer: NVIDIA is seeking an elite ASIC Verification Engineer to verify the design… position, you will be working on verifying ASIC design using advanced verification methodologies. You are expected to understand…
  • 4.0
    VeriSilicon Holdings Co., Ltd. – San Jose, CA
    EASY APPLY
    Est. Salary $89k-$118k
    8 days ago 8d
    skills in Verilog Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design… micro-architecture, implementation (using Verilog), and verification. Expected skills: 5+ years hands-on experience with…
  • 3.6
    Redolent, Inc – Santa Clara, CA
    EASY APPLY
    10 days ago 10d
    requirement with our direct client: Title: Specman Engineer (ASIC Verification) Location: Santa Clara, CA Duration: 6+ months… At least 5+ Yr hands-on ASIC verification experience; Wireless communication/DSP chip verification experience is must;…
  • 3.7
    Marvell Technology – Santa Clara, CA
    24 days ago 24d
    motivated engineer to join our team. - BS/MS in EE, CE, CS, required. - A minimum 5 years of experience with digital ASIC design… developing corresponding verification plans. Designing and developing components of our verification environment using UVM, System…
  • 4.4
    Embedded Resource Group, Inc. – Mountain View, CA
    30+ days ago 30d+
    ASIC/FPGA Design Verification Engineer Seeking design verification engineer for verification of FPGA design. Required… Required Skills: • ASIC or FPGA design verification • At least 2 + UVM projects in past • System Verilog • Scripting – Ruby, Perl…
  • 3.0
    Innovative Logic Inc. – San Jose, CA
    Est. Salary $92k-$126k
    5 days ago 5d
    We are looking for UVM Verification engineer with the followings skills. You have to spend most of the time writing test benches… SystemVerilog, UVM, C, Verilog · Good understanding of new verification concepts Nice to Have o ARM SOC knowledge, AHP, APB…
  • 3.1
    Aquantia – San Jose, CA
    EASY APPLY
    Est. Salary $78k-$98k
    27 days ago 27d
    understanding of digital design verification methodologies and tools including: • Expertise in creating verification infrastructure using… Responsibilities: • Responsible to define and implement verification architectures for mixed signal data communications semiconductors…
  • Advanced Technology Search – San Jose, CA
    Est. Salary $91k-$142k
    13 days ago 13d
    Description ASIC/IP Verification Engineer ASIC/Layout Design Engineer: Oversees definition, design, verification, and documentation… development, part of the ASIC solution for storage applications. They are looking for a Senior Verification Engineer, who will be a key…
  • 3.3
    Toshiba America Business Solutions – San Jose, CA
    Est. Salary $87k-$120k
    20 days ago 20d
    the verification team to develop Flash Controller H/W architecture(s) and new ASIC design(s) with functional verification and… and Design Center SoC development team, the Director, ASIC verification is responsible for creating innovative SSD controllers…
  • 3.7
    Marvell Technology – Santa Clara, CA
    Est. Salary $92k-$117k
    24 days ago 24d
    closure. * MS in EE with 3 years of work experience in SOC/ASIC/IP development. * Must have knowledge and experience of HDL… Knowledge of UVM and System Verilog is required. * Background in ASIC implementation including lint, CDC, synthesis, formal and static…
  • 3.7
    Intel – San Jose, CA
    Est. Salary $90k-$116k
    1 days ago 20hr
    understanding of the ASIC development flow. Proven track record in development and Experience with IP architecture, verification, and rollout… Bachelor's degree in Electrical Engineering or equivalent with at least 7 years of experience in ASIC development, with a complete…
  • 3.0
    Toshiba – San Jose, CA
    Est. Salary $65k-$92k
    30+ days ago 30d+
    will own the whole or parts of sub modules verification and/or full chip verification in SSD controllers. Such modules are SATA… controllers. Define and develop verification architecture and methodology Writing verification plans, tests, and building random…
  • 2.7
    GLOBALFOUNDRIES – Santa Clara, CA
    2 days ago 2d
    teams as they develop SoC solutions utilizing CMOS cell-based ASIC technologies. Essential Responsibilities: Implementation… design automation software and flows to ensure high quality ASIC designs Gather requirements and product specifications from…
  • 3.5
    Mobiveil – Milpitas, CA
    EASY APPLY
    Est. Salary $67k-$94k
    15 days ago 15d
    on ASIC/SOC/IP Functional Verification Experience Verification Expertise in System Verilog Expert in Verification methodologies… LZ77 compression algorithm) Verification. Data compression Experince developing Verification components from scratch…
  • 3.3
    Toshiba America Business Solutions – San Jose, CA
    Est. Salary $65k-$91k
    8 days ago 8d
    Linux environments Other: 7+ years of SoC/ASIC verification experience Hands on experience using UVM SSD controller… Development of the verification IPs and integration in the verification platform Definition of the verification plan in collaboration…
  • 3.1
    OmniVision Technologies – Santa Clara, CA
    Est. Salary $100k-$138k
    20 days ago 20d
    experience in ASIC design flow: RTL coding, simulation, synthesis, static timing analysis, formality verification, DFT. Extensive… integration and verification. CMOS image sensor array/analog related timing control design and verification. Chip bring-up,…
  • 3.3
    Sony Electronics – San Jose, CA
    Est. Salary $90k-$121k
    23 days ago 23d
    develop and implement solutions Familiarity with ASIC/SoC design/verification methodologies Ability to write detailed and clear… leader in image sensors, is seeking a staff VLSI/ASIC logic Design Engineer to work on our next generation image sensor products…
  • 3.6
    Fortive – Santa Clara, CA
    Est. Salary $95k-$125k
    11 days ago 11d
    Job Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers… Requirements o Internship/industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity…
  • 3.3
    Toshiba America Business Solutions – San Jose, CA
    Est. Salary $65k-$91k
    9 days ago 9d
    will own the whole or parts of sub modules verification and/or full chip verification in SSD controllers. Such modules are SATA… controllers. Define and develop verification architecture and methodology Writing verification plans, tests, and building random…
  • 3.5
    Broadcom – Santa Clara, CA
    Est. Salary $105k-$140k
    2 days ago 2d
    Create verification environments using Systemverilog and Universal verification methodology-UVM for Panel Scan Engine-PSE, Hardware… interfaces. Integrate Matlab and C model into SoC and Block level verification Environments. Develop test plans and coverage metrics from…
  • 4.0
    Intrinsix – San Jose, CA
    Est. Salary $94k-$124k
    1 days ago 14hr
    mixed-mode ASIC design and ASIC/SoC development. Applicant must have a Master’s Degree or PhD in Electrical Engineering, Computer… growing a team of engineers. Qualifications: 15+ years of experience in transistor-level design and verification of Mixed-Signal…
  • 3.8
    Cisco Systems – San Jose, CA
    Est. Salary $101k-$141k
    9 days ago 9d
    1208196 New Title: ASIC Physical Design Engineer Location: San Jose, CA WHO YOU'LL WORK WITH… as Physical Design lead in San Jose, CA. You will work with ASIC Front-end teams to understand chip architecture and drive physical…
  • Cohere Technologies, Inc – Santa Clara, CA
    Est. Salary $92k-$119k
    5 days ago 5d
    detailed design and verification. This position reports directly to the Director of FPGA/ASIC Engineering Required Qualifications… networking protocols Multiple ASIC tapeouts. Experience with Xilinx FPGAs. 7+ years of experience in ASIC/FPGA design. Education…
  • 3.8
    Cisco Systems – San Jose, CA
    9 days ago 9d
    with minimal oversight. You are an ASIC Design for Test engineer with 10+ years of related work experience with a… 1208197 New Title: Technical Lead, ASIC Design for Test Location: San Jose, CA WHO YOU'LL WORK…
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