Design Verification Engineer Jobs in Santa Clara, CA | Glassdoor
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Design Verification Engineer Jobs in Santa Clara, CA

  • 3.8
    Marvell Technology – Santa Clara, CA
    Est. Salary $87k-$111k
    NEW
    requires a minimum of 7 years of experience in the verification of chip designs. Masters degree in EE is preferred. Experience… requires a minimum of 7 years of experience in the verification of chip designs. Masters degree in EE is preferred. Experience…
  • 4.8
    Cypress HCM – Santa Clara, CA
    27 days ago 27d
    DesignVerificationEngineer The DesignVerificationEngineer is supporting our Client’s DNA Sequencing unit. You will be responsible… integrate chip functional and test designverification activities with Design Architecture, Physical Design, System, and software processes…
  • 3.5
    Synapse Design – San Jose, CA
    EASY APPLY
    Est. Salary $93k-$117k
    5 days ago 5d
    UVM · Utilize advanced verification techniques · Write tools and scripts to enhance the verification process Qualifications… Some level of CPU Core processor based verification · Experience with advanced verification techniques like constrained random generation…
  • 4.6
    TalentBurst – Santa Clara, CA
    11 days ago 11d
    experience, with several complete and successful FPGA design/verification cycles under his/her belt Strong SystemVerilog/UVM,… Responsibilities will include developing the verification environment; developing test plans and verifying the function of the…
  • 3.1
    Huawei – Santa Clara, CA
    Est. Salary $101k-$128k
    9 days ago 9d
    innovation to deliver a better future... faster. DesignVerificationEngineers at various levels for a family of high-end 64 bit… Oversee the design/DV environment issues. 4-10 years of designverification experience in micro-processor design, with programming…
  • 4.0
    Roche – Santa Clara, CA
    Est. Salary $107k-$136k
    19 days ago 19d
    of IP/Chip designverification tools and methodologies Outstanding hands-on experience in the entire verification process, from… experience. 8+ years of industry experience in chip and IP DesignVerification Experience in creating and coordinating test plans…
  • 3.0
    a2z Development Center – Cupertino, CA
    Est. Salary $115k-$144k
    25 days ago 25d
    Develop multi-faceted verification/validation strategies and plans that include advanced designverification, FPGA, emulation, software… semiconductor designverification experience including System Verilog, UVM, assertions and coverage driven verification. · Experience…
  • 3.6
    Broadcom – Santa Clara, CA
    Est. Salary $118k-$150k
    19 days ago 19d
    and other new initiatives by working on designverification. As a verificationengineer, your responsibilities will include:… Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup. Evaluate latest verification methodologies…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $142k-$190k
    20 days ago 20d
    Responsible for verification of design, architecture, golden models and micro-architecture using advanced verification methodologies… for understanding the design and implementation, define the verification scope, develop the verification infrastructure (Transactors…
  • 3.6
    Amazon – Cupertino, CA
    Est. Salary $89k-$113k
    25 days ago 25d
    Develop multi-faceted verification/validation strategies and plans that include advanced designverification, FPGA, emulation, software… semiconductor designverification experience including System Verilog, UVM, assertions and coverage driven verification. · Experience…
  • 4.4
    Google – Mountain View, CA
    Est. Salary $98k-$123k
    28 days ago 28d
    interacting with designengineers to identify important verification scenarios. Create a constrained-random verification environment… with designengineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes…
  • Tekberry – Santa Clara, CA
    Est. Salary $88k-$137k
    19 days ago 19d
    is looking for a highly qualified and motivated DesignVerificationEngineer to work on-site with our client, a Global Telecommunications… environment. Job Description: Help the Pre-Silicon designverification team in verifying the core-level memory-subsystem blocks…
  • 3.5
    Barefoot Networks, Inc. – Santa Clara, CA
    EASY APPLY
    Est. Salary $84k-$108k
    24 days ago 24d
    Responsibilities: Senior DV engineer responsible for defining and implementing verification methodology and verifying in any… visionaries, experienced technologists and engineers who have created a blueprint for designing and operating the worlds fastest and…
  • 4.2
    ASIC North, Inc. – San Jose, CA
    Est. Salary $112k-$143k
    21 days ago 21d
    application engineer Creating and maintaining regression test suites Involved in defining and driving design and verification methodologies… chip-level) simulations according to the verification plan Preparing and holding designverification reviews and report back the failing…
  • 3.7
    Xilinx – San Jose, CA
    Est. Salary $119k-$150k
    5 days ago 5d
    Xilinx FDST Verification group is looking for a Staff DesignVerificationEngineer to provide technical leadership and contribution… Electrical Engineering, Computer Engineering or Computer Science. Require hands on experience with verification of state of…
  • 4.0
    Arista Networks – Santa Clara, CA
    EASY APPLY
    Est. Salary $51k-$66k
    7 days ago 7d
    Electrical DesignVerification Tests Participate on project teams of engineers involved in specification, design, development… Computer Engineering 0-5 years of experience in Electrical DesignVerification Testing (EDVT) Hands on capability to design and…
  • 3.6
    Redolent, Inc – Sunnyvale, CA
    Est. Salary $65k-$83k
    12 days ago 12d
    requirement with our direct client: Title: DesignVerificationEngineer Location: Sunnyvale, CA Duration: 6 to 12+ months… state of the art of verification techniques, including assertion and metric-driven verification. Verification experience AXI, NoC…
  • 3.7
    Intel – San Jose, CA
    Est. Salary $100k-$125k
    26 days ago 26d
    in the future for FPGAs, PSG is looking for great DesignVerificationEngineers to join our team. Intel Programmable Solutions… experience in SoC/IP design, in functional verification of digital circuit and/or front to back digital design flow (or similar)…
  • 4.4
    VeriSilicon Holdings Co., Ltd. – San Jose, CA
    EASY APPLY
    Est. Salary $89k-$120k
    7 days ago 7d
    Verilog), and verification. Expected skills: 5+ years hands-on experience with focus on front-end complex RTL design Programming… familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation) Highly motivated…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    Est. Salary $85k-$117k
    14 days ago 14d
    years experience in the field of DesignVerification is a must Familiar with SoC verification skills including UVM and C-based… Develop and manage the sub-system and system level verification strategy and design for testing methodology Need to execute detailed…
  • 3.9
    Cisco Systems – San Jose, CA
    Est. Salary $101k-$127k
    7 days ago 7d
    in the lab. Mentor and enable other engineers. Lead and oversee designverification efforts of a cluster of blocks. Skills… Experience in high-performance ASIC verification. Good understanding of ASIC design and verification methodologies and flows. Hands-on…
  • 4.5
    Technology Search International – Santa Clara, CA
    Est. Salary $92k-$118k
    22 days ago 22d
    I have a Career Opportunity for an experienced ASIC VerificationEngineer who has experience with SoCs and ASICs and verifying… / SoC Verification experience with SV/UVM environments. Must have advanced knowledge of CPU & SoC architecture/design. BSEE…
  • 3.7
    Qualcomm – San Jose, CA
    Est. Salary $107k-$137k
    11 days ago 11d
    Job Id E1956947 Job Title PHY DesignVerificationEngineer Post Date 07/13/2017 Company Division… architecture, design, implementation, and verification of next-generation Wireless LAN devices. This is for a DesignVerification position…
  • 4.0
    Roche – Santa Clara, CA
    Est. Salary $105k-$133k
    NEW
    industry experience in ASIC / FPGA designverification Hands-on experience in the entire verification process, from test plan to… FPGA-based co-simulation, and emulation platforms for DesignVerification Working knowledge of SystemVerilog & Object Oriented…
  • 3.5
    Synapse Design – Santa Clara, CA
    EASY APPLY
    Est. Salary $93k-$117k
    4 days ago 4d
    UVM · Utilize advanced verification techniques · Write tools and scripts to enhance the verification process Qualifications… UVM · Some level of processor based verification · Experience with advanced verification techniques like constrained random generation…
  • 3.7
    Xilinx – San Jose, CA
    Est. Salary $108k-$136k
    5 days ago 5d
    Wireless FDST Verification group is looking for a Senior DesignVerificationEngineer to contribution on FPGA block… full chip verification. The individual will help design, develop and use simulation and/or formal based verification environments…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    Est. Salary $90k-$114k
    NEW
    As a SoC VerificationEngineer, the successful candidate will be responsible for functional verification of high performance SSD… with modern verification technology, such as UVM. Responsibility includes understanding functionality of SoC designs, developing…
  • 3.7
    Intel Corporation – San Jose, CA
    Est. Salary $93k-$118k
    NEW
    Hire Senior DesignVerificationEngineer Job Description As a Senior DesignVerificationEngineer for high speed digital… will create verification architecture and test-plan specifications. You will be responsible for designverification of a complex…
  • 4.1
    Inphi Corporation – Santa Clara, CA
    20 days ago 20d
    for a Senior Staff VerificationEngineer. The candidate must have proven record of verifying complex designs leading to successful… architects and designengineers. Responsibilities include: Technical leadership, own chip and block level verification. Define…
  • 4.1
    Integrated Resources – Santa Clara, CA
    Est. Salary $99k-$125k
    5 days ago 5d
    the Pre-Silicon designverification team in verifying the core-level memory-subsystem blocks. The engineer will be responsible…
  • 4.0
    Apple – Santa Clara, CA
    Est. Salary $119k-$148k
    19 days ago 19d
    chip design cycle to drive signoff closure for tapeout Managing schedules and supporting cross-functional engineering effort… As a member of the physical design team, you would be responsible for: Interfacing with the CAD/Technology teams for flow…
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