Senior ASIC Design Engineer Jobs in Santa Clara, CA | Glassdoor
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Senior ASIC Design Engineer Jobs in Santa Clara, CA

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  • 4.0
    VeriSilicon Holdings Co., Ltd. – San Jose, CA
    EASY APPLY
    Est. Salary $91k-$121k
    4 days ago 4d
    -end complex RTL design Programming skills in Verilog Must be familiar with all stages of the ASIC design flow (including specification… of computer graphics and low-power design techniques a plus Experience of GPU shader design a plus…
  • 4.9
    Light.co – Palo Alto, CA
    Est. Salary $99k-$128k
    1 days ago 1d
    change photography. As our ASIC Design Engineer, you will be responsible for the full ASIC design cycle for our game-changing… is needed to create an ASIC from conception to implementation Work with Light partners on ASIC design What you bring to Light…
  • 3.8
    Cisco Systems – San Jose, CA
    Est. Salary $113k-$150k
    4 days ago 4d
    forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. P4… domain-specific languages. - Ability to communicate with ASIC engineers. Why Cisco We connect everything: people, processes, data…
  • 4.4
    NVIDIA – Santa Clara, CA
    Est. Salary $138k-$185k
    7 days ago 7d
    We're now looking for a Senior ASIC Verification Engineer:Nvidia’s invention of the GPU 1999 sparked the growth of the PC gaming… 'll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading…
  • 3.8
    Nokia – Sunnyvale, CA
    4 days ago 4d
    of conventional design techniques. As a Senior ASIC Designer, you will effectively communicate your design ideas to fellow… requirements: • 8 years of ASIC digital design experience • Experienced the full cycle production level ASIC design and tape out •…
  • 3.2
    Seagate Technology – Fremont, CA
    Est. Salary $116k-$155k
    11 days ago 11d
    innovation, seeks an ASIC Design Engineer for an exciting role at our new Freemont Design Center. The Senior Staff Engineer position is… understanding of ASIC design methodology, high speed CMOS circuit and logic design knowledge including arithmetic unit designs such as…
  • 4.4
    NVIDIA – Santa Clara, CA
    21 days ago 21d
    We are now looking for a Senior ASIC Power Engineer: In this role you will be responsible for crafting and implementing the… Tesla products. As a senior team member, you will collaborate closely with Architecture, Software, ASIC, VLSI, DFT, Layout, and…
  • 3.5
    Broadcom – Santa Clara, CA
    Est. Salary $102k-$137k
    25 days ago 25d
    and Gate simulations and resolve them by working with design engineers. Create low power testcases using UPF or CPF to verify… Systemverilog and Universal verification methodology-UVM for Panel Scan Engine-PSE, Hardware Accelerator Blocks and SoCs with embedded CPUs…
  • 3.1
    Tektronix – Santa Clara, CA
    Est. Salary $112k-$146k
    7 days ago 7d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • 2.9
    Avago Technologies – Santa Clara, CA
    Est. Salary $103k-$134k
    18 days ago 18d
    work with design engineers to verify fixes. ○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. ○… Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: ○ Architect block…
  • 3.1
    Fortive – Santa Clara, CA
    Est. Salary $95k-$124k
    6 days ago 6d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • 2.9
    Fluke Corporation – Santa Clara, CA
    Est. Salary $92k-$120k
    7 days ago 7d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • 3.3
    Toshiba America Business Solutions – San Jose, CA
    Est. Salary $71k-$93k
    15 days ago 15d
    Participate in the SSD Controller ASIC HW & FW specification development Detailed module design and functional verification Responsible… Storage Research and Design Center SoC development team, candidate will be responsible for developing module designs for the SSD controller's…
  • GigPeak – San Jose, CA
    EASY APPLY
    Est. Salary $107k-$156k
    4 days ago 4d
    Senior ASIC Design Engineer (Job Code WL) REPORTS TO: Director of ASIC Engineering LOCATION: San Jose, CA CLASSIFICATION:… currently seeking a Senior ASIC Design Engineer. Essential Duties and Responsibilities Management of ASIC design development Meet…
  • Approgence – San Jose, CA
    Est. Salary $79k-$105k
    9 days ago 9d
    Job Title : Senior ASIC/ RTL Design Engineer with DSP Job Location : San Diego & San Jose, CA Job Description : This… perform bit-exact simulation. - Modem ASIC Design team is working with physical design engineer to deliver netlist, spec timing constraints…
  • 2.5
    SK Hynix Memory Solutions – San Jose, CA
    Est. Salary $93k-$121k
    15 days ago 15d
    Descriptions: The ASIC Design Engineer will be working on the leading edge SSD controller IP design from architecture to production… support physical design and system level analysis. Qualifications: * BS, MS, or PhD in Electrical Engineering with 5-10 years…
  • 3.7
    Intel – Santa Clara, CA
    Est. Salary $90k-$125k
    14 days ago 14d
    NGS) 5G BBIC team, we are looking for a senior level Front End Design Automation Engineer to join the 5G Mobile Wireless Technology… Frontend Design Automation Engineer, you will be responsible for driving methodology, and productivity improvements in design flows…
  • 3.0
    Toshiba – San Jose, CA
    Est. Salary $66k-$92k
    30+ days ago 30d+
    tests, and building random/directed test benches. Working with design team and firmware team. Provides technical guidance to other…
  • 3.7
    Brocade – San Jose, CA
    Est. Salary $121k-$170k
    1 days ago 17hr
    Review design, code, unit tests from other engineers and ensure they meet good quality standards Mentor junior engineers in the… either off the shelf chips (e.g. Broadcom) or in house built ASICs Knowledge of L2 and L3 protocols and forwarding aspects…
  • 3.6
    Qualcomm – Santa Clara, CA
    Est. Salary $119k-$157k
    18 days ago 18d
    Job Id E1950488 Job Title Digital Design Engineer - Mixed-Signal Power Management ASICs (Staff to Lead level) Post Date… you have digital design experience and are interested in the design of digital logic for mixed-signal ASICs, this opportunity…
  • Advanced Technology Search – San Jose, CA
    Est. Salary $91k-$142k
    14 days ago 14d
    Job Description ASIC/IP Verification Engineer ASIC/Layout Design Engineer: Oversees definition, design, verification, and… development, part of the ASIC solution for storage applications. They are looking for a Senior Verification Engineer, who will be a key…
  • 4.4
    NVIDIA – Santa Clara, CA
    1 days ago 16hr
    Electrical Engineering required, advanced degrees (MS, PhD) a plus. Looking for Senior & Lead ASIC Design engineers with 5-15… ideal candidate will also be familiar with all stages in the ASIC design flow including emulation, prototyping, DFT, timing analysis…
  • Precision ERP – San Jose, CA
    Est. Salary $70k-$100k
    30+ days ago 30d+
    Position: Senior Design Engineer - Digital IP Location: San Jose, CA Required: - BS/MS in Electrical Engineering or relevant… experience in design of complex digital IP, and/or SoC integration - Skills in RTL implementation & synthesize design constrained…
  • Approgence – Santa Clara, CA
    16 days ago 16d
    looking for a senior expert in SoC Physical Design and RTL Delivery Management for advanced modem Baseband ASIC. - Provide technical… Job Title : SoC Physical Design and RTL Delivery Lead / Principal Engineer Job Location : Santa Clara, CA Job Description…
  • 3.3
    Toshiba America Business Solutions – San Jose, CA
    Est. Salary $66k-$92k
    22 days ago 22d
    California City: San Jose Area of Interest: Engineering Equal Opportunity Employer Minorities/Women/Protected… Job Title: TAEC - Eng Design Principal-110213 Requisition Number: 1047 Job Description Toshiba America…
  • 3.7
    Intel Corporation – Santa Clara, CA
    Est. Salary $85k-$114k
    23 days ago 23d
    experience in CMOS Design, ASIC Design, VLSI and Device Physics - Experience interfaceing with engineers, senior managers and stakeholders… Electrical Engineering or Computer Engineering Computer Science with at least 10 years of experience in IC/ASIC Design or Computer…
  • 2.5
    SK Hynix Memory Solutions – San Jose, CA
    Today 2hr
    power analysis). Demonstrated capability to design major blocks involving ASIC, IPs, logic, and FPGAs. Excellent logic developer… Electrical or Computer Engineering, BS or graduate level. Excellent experience and knowledge in FPGA design flow and tools, preferably…
  • 3.6
    Xilinx – San Jose, CA
    Est. Salary $105k-$141k
    4 days ago 4d
    ACE, CHI protocols Experience in designing blocks for an SOC Experience in integrating ASIC IP into SOC Experience with automation… Xilinx has an opening for a Hardware Design Engineer in the SOC Design team. This team is designing the future generations high-performance…
  • 3.8
    Dialog Semiconductor – Campbell, CA
    Est. Salary $82k-$113k
    8 days ago 8d
    continued growth, we seek a Senior Digital Design Engineer. The role Working in the Digital Design - Power Conversion Business… for • 8+ years of direct experience in ASIC/IC design with deep knowledge of whole IC design flow from RTL coding and verification…
  • 3.7
    Oclaro – San Jose, CA
    Est. Salary $111k-$163k
    30+ days ago 30d+
    Commodity Manager ASICs Oclaro, Inc. (Nasdaq: OCLR), is a leader in optical components, modules and subsystems for the core… Management team responsible for the strategic direction of the ASICs commodity. As such, this position will "own" the commodity and…
  • 3.7
    Intel – Santa Clara, CA
    Est. Salary $102k-$138k
    8 days ago 8d
    tools; UVM/OVM verification methods -Synopsys ASIC design tools - VCS simulator, Design Compiler, IC Compiler -Formal verification… corresponding design modifications and optimizations as required to achieve power and performance targets. -Execution of ASIC logic synthesis…
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