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Senior ASIC Design Engineer Jobs in Santa Clara, CA

180 Jobs

  • 4.4
    VeriSilicon Holdings Co., Ltd. – San Jose, CA
    EASY APPLY
    $92k-$124k(Glassdoor est.)
    HOT
    front-end complex RTL design Programming skills in Verilog Must be familiar with all stages of the ASICdesign flow (including… of computer graphics and low-power design techniques a plus Experience of GPU shader design a plus…
  • 5.0
    Tarana Wireless – Santa Clara, CA
    EASY APPLY
    $94k-$126k(Glassdoor est.)
    14 days ago 14d
    PRIMARY RESPONSIBILITY: The SeniorASICEngineer will work on complex ASIC and FPGA designs for our point to multipoint wireless… RTL design of digital circuits using VHDL or System Verilog Frontend design development and integration of large ASIC designs…
  • 4.3
    NVIDIA – Santa Clara, CA
    $127k-$166k(Glassdoor est.)
    HOT
    now looking for a SeniorASICDesignEngineer: NVIDIA is seeking best-in-class ASICDesignEngineers to design and implement the… BS or MS in electrical engineering or computer engineering 3+ years of experience working on ASICdesign and development Experience…
  • 4.0
    Apple – Santa Clara, CA
    $124k-$170k(Glassdoor est.)
    28 days ago 28d
    SeniorASICDesignEngineer - Fabric Job Number: 52464960 Santa Clara Valley, California, United States Posted: Jan. 9,… position requires thorough knowledge of the ASICdesign flow, front end RTL coding and Design verification, synthesis, scripting and…
  • 4.0
    Apple – Santa Clara, CA
    $124k-$170k(Glassdoor est.)
    NEW
    SeniorASICDesignEngineer - Cache Job Number: 113334333 Santa Clara Valley, California, United States Posted: Dec. 19… Qualifications The ideal candidate will have 5+ years of ASICdesign experience: 5+ years of development of memory system.…
  • 4.3
    NVIDIA – Santa Clara, CA
    $135k-$180k(Glassdoor est.)
    NEW
    NVIDIA is seeking an outstanding ASIC Verification Engineer to verify the design and implementation of the world’s leading SoC's… be doing: As a Senior Verification Engineer at NVIDIA, you will be responsible for verifying the design, architecture and micro-architecture…
  • 3.9
    Xilinx – San Jose, CA
    6 days ago 6d
    are looking for highly motivated ASICDesign Verification Engineers to verify complex ASICdesign and implementation of the world… BS w/ 10 years (MS preferred) in Electrical Engineering, Computer Engineering or Computer Science. · Proven track record…
  • 3.6
    Broadcom – Santa Clara, CA
    $106k-$143k(Glassdoor est.)
    NEW
    work with designengineers to verify fixes. ○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. ○… Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: ○ Architect block…
  • 4.3
    NVIDIA – Santa Clara, CA
    $135k-$180k(Glassdoor est.)
    6 days ago 6d
    looking for a Senior GPU ASIC Verification Engineer: NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the… architects, ASICdesigners, and other verification engineers to craft and deliver the best performing GPUs to market. What we need…
  • 3.6
    AMD – Santa Clara, CA
    $106k-$147k(Glassdoor est.)
    5 days ago 5d
    development team at AMD Sunnyvale for ASIC Physical Designengineer. You will join us as Staff Engineer / Member of Technical Staff.… multi-site engineers and managers Qualifications 8+ years' experience with MSEE or MSCE in ASIC Physical Design from RTL…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    $136k-$178k(Glassdoor est.)
    8 days ago 8d
    Digital Processor ASIC/FPGA Designer: The Senior Staff ASIC/FPGA DesignEngineer will be working in the RF Center of Excellence… the effort to meet the customer requirements. The Senior Staff FPGA/ASICdesigner will provide technical support across the enterprise…
  • 2.9
    Avago Technologies – Santa Clara, CA
    $108k-$141k(Glassdoor est.)
    NEW
    work with designengineers to verify fixes. ○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. ○ Replicate… Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: ○ Architect block…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    $89k-$120k(Glassdoor est.)
    8 days ago 8d
    Digital Processor ASIC/FPGA Designer: The SeniorASIC/FPGA DesignEngineer will be working in the RF Center of Excellence (… (RF CoE). The Senior FPGA/ASICdesigner will provide technical support to the RF COE ASIC/FPGA design Team. The individual…
  • 3.8
    Fortinet – Sunnyvale, CA
    $134k-$176k(Glassdoor est.)
    27 days ago 27d
    performance ASICdesign from specification to system bring up; FPGA design experience to verify large scale ASIC Networking… Responsibilities: ASIC architecture research, analysis and specification High performance and high quality ASICdesign from specification…
  • 3.3
    cPacket Networks – San Jose, CA
    $87k-$121k(Glassdoor est.)
    22 days ago 22d
    expected to be able to design, implement and test both unit level modules and higher level architecture designs. Candidates should… should be comfortable understanding tradeoffs in the design and be able to articulate them. This role requires being able to develop…
  • 4.2
    CyberCoders – San Jose, CA
    7 days ago 7d
    SeniorASIC/FPGA Verification Engineer If you are a Senior FPGA ASIC verification Engineer with experience, please read on!… test generation and checking. So, if you are a Senior FPGA ASICEngineer with experience, please apply today! Applicants…
  • Approgence – San Jose, CA
    $82k-$113k(Glassdoor est.)
    28 days ago 28d
    Job Title : SeniorASIC/ RTL DesignEngineer Job Location : San Diego & San Jose, CA Job Description : This is a… perform bit-exact simulation. Modem ASICDesign team is working with physical designengineer to deliver netlist, spec timing constraints…
  • 3.5
    Micron Technology – Milpitas, CA
    $103k-$131k(Glassdoor est.)
    7 days ago 7d
    including more seniorengineers and management teams. Requirements: Experience working with CMOS ASICdesign & foundry teams… US Company: Micron Req. ID: 98441 SeniorASIC Product Engineer Why this position matters Micron Technology…
  • 3.6
    TSMC North America – San Jose, CA
    NEW
    experience. o For senior position, 5+ years of proven tapeout records is preferred. · Proven APR hands-on tapeout ASIC experiences… /high-performance ASIC chips. Requirements: · Education: o Master’s degree in Electrical Engineering or Computer Science…
  • 3.2
    Western Digital – Milpitas, CA
    $110k-$150k(Glassdoor est.)
    7 days ago 7d
    LAUNCH ASIC Development SeniorEngineer Location: Milpitas, California, United States Req ID: 9000001230 Apply… analog or digital design and/or verification ASIC digital or mixed signal design and/or verification FW design and/or verification…
  • 3.8
    Intel – Santa Clara, CA
    $98k-$137k(Glassdoor est.)
    NEW
    multi-million gate ASICs in advance process nodes Experience with RTL-to-GDS design flows IC Compiler, etc. for advance process nodes… Computer Engineering plus at least 4+ years of industry experience in the following areas: RTL & lower level design of multi-million…
  • 3.7
    Cavium – San Jose, CA
    $92k-$121k(Glassdoor est.)
    NEW
    processors. You will work directly with senior members of the ASIC team to learn and design state of art high speed digital systems. Responsibilities… As a new graduate engineer, you would contribute as a designengineer developing the next-generation of multi-core processors.…
  • 4.0
    Microsoft – Sunnyvale, CA
    $139k-$183k(Glassdoor est.)
    Today 11hr
    successful core or IP designs in complex large ASICs in leading-edge technology Experience in chip design/tapeout reviews, understanding… leader in the design of world class entertainment devices. We are looking for a senior level design integration engineer to work in…
  • 3.2
    Western Digital – Milpitas, CA
    28 days ago 28d
    Senior Manager - ASICDesign Verification Location: Milpitas, California, United States Req ID: JR-0000027569… what’s possible. The ASICDesign Verification Manager will manage a team of engineers performing verification of RTL,…
  • 3.6
    OmniVision Technologies – Santa Clara, CA
    $105k-$145k(Glassdoor est.)
    28 days ago 28d
    Sr./Staff Analog DesignEngineerSenior Analog DesignEngineer Analog Mixed-Signal DesignEngineer Sr./Staff… production, to customer support. In-depth hands-on experience in ASICdesign flow: RTL coding, simulation, synthesis, static timing analysis…
  • 3.4
    Aruba Networks – Santa Clara, CA
    $154k-$218k(Glassdoor est.)
    Today 11hr
    designs, programs, debugs and modifies switch software operating system and features (e.g., low level software and ASIC drivers… Apply Senior Switching Platform Engineer Date posted 09/28/2017 Location Santa Clara, California Analyzes, designs…
  • 3.9
    Palo Alto Networks – Santa Clara, CA
    $75k-$96k(Glassdoor est.)
    NEW
    hardware including Board, FPGA and ASIC. You will be working on our Board Hardware team who designs and tests printed circuit assemblies… Requirements: To apply, you must be a rising senior in an Electrical Engineering major, returning to school in the fall. You must…
  • 4.0
    Apple – Santa Clara, CA
    $147k-$196k(Glassdoor est.)
    NEW
    Description As a senior IP Designengineer you will have responsibilities spanning all aspects of multimedia IP design: Collaborate… Senior Multimedia/DMA IP DesignEngineer Job Number: 52394527 Santa Clara Valley, California, United States Posted: Dec…
  • 2.9
    Seagate Technology – Fremont, CA
    $102k-$135k(Glassdoor est.)
    22 days ago 22d
    with senior internal and external personnel in own area of expertise. Requirements: The Sr. ASIC Mask DesignEngineer is not… directed by ASICDesignEngineers. The role will have circuit / block-level ownership responsibility with ASICEngineering and will…
  • 2.9
    Seagate Technology – Fremont, CA
    $103k-$138k(Glassdoor est.)
    23 days ago 23d
    171324 Senior Staff ASICDesign and Verification Engineer (Open) Seagate delivers advanced digital storage solutions to meet… Experience with advance ASICdesign verification methodology such as UVM and VMM flow. Experience with all popular ASIC EDA tools like…
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